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TNETX15VE 数据表(PDF) 93 Page - Texas Instruments |
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TNETX15VE 数据表(HTML) 93 Page - Texas Instruments |
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93 / 113 page  TNETX15VE VLAN-ENGINE ADDRESS-LOOKUP DEVICE SPWS028B – APRIL 1997 – REVISED SEPTEMBER 1997 93 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH High-level output voltage VCC–0.6 V VOL Low-level output voltage 0.4 V IOZ High impedance state output current VO = VCC 20 µA IOZ High-impedance-state output current VO = 0 –20 µA IIH High-level input current VI = VI(MAX) –20 µA IIL Low-level input current VI = GND 20 µA ICC Supply current, 3.3 V 360 mA ICC(5V) Supply current, 5 V 1 mA timing requirements (see Note 6 and Figure 18) external SRAM read cycle NO. MIN MAX UNIT 1 tc(R) Cycle time, read 40 ns 2 tsu(ED) Setup time, ED15–ED0 valid before OSCIN ↑ 11 ns 3 th(ED) Hold time, ED15–ED0 valid after OSCIN ↑ 3 ns operating characteristics over recommended operating conditions (see Note 6 and Figure 18) external SRAM read cycle NO. PARAMETER MIN MAX UNIT 4 td(EA) Delay time, from OSCIN ↑ to EA20–EA0 valid 16 ns 5 td(EOE)1 Delay time, from OSCIN ↓ to EOE↓ 11 ns 6 td(EOE)2 Delay time, from OSCIN ↑ to EOE↑ 3 11 ns 7 td(EA) Delay time, from EOE ↑ to EA20–EA0 transition (change) 0 ns NOTE 6: td(EA) and tsu(ED) are further characterized over a restricted voltage range on the VCC (3.3 V) rail to allow the use of 15-ns SRAMs. With the values listed, which are valid over a 3.0 V to 3.6 V range (VCC), 12-ns SRAMs are required to meet the system timing. If the VCC (3.3 V) is restricted to the range of 3.4 V to 3.6 V, td(EA) is reduced to 14 ns, and tsu(ED) is reduced to 10 ns. This allows the use of 15-ns SRAMs. Although the operating voltage range of the VCC rail (3.3 V) has a higher minimum, this additional data applies over the operating temperature range of the TNETX15VE. Z 5 1 6 Z 3 EA20–EA0 (output) EWE (output) EOE (output) ED15–ED0 (input) OSCIN (input) 2 Valid 4 4 Valid Valid 7 Figure 18. External SRAM Read Cycle |
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