TNETX15VE datasheet(54/113 Pages) TI1

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TNETX15VE

VLAN-ENGINE ADDRESS-LOOKUP DEVICE

SPWS028B – APRIL 1997 – REVISED SEPTEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

decoding the destination address (DA) and source address (SA) from the DRAM bus

The TNETX3150/TNETX3150A writes data to the DRAM buffers in a specific format (refer to the

TNETX3150/TNETX3150A data sheet for additional information on this format). The TNETX15VE recognizes

this format to determine the correct destination and source addresses. The format for the DA and the SA is

shown in the following:

CYCLE

BIT

DA23–DA16

DA31–DA24

DA39–DA32

DA47–DA40

SA39–SA32

SA47–SA40

DA7–DA0

DA15–DA8

SA7–SA0

SA18–SA8

SA23–SA16

SA31–SA24

The node addresses are transmitted on the DRAM bus in the Ethernet native data format. This is the same

format in which the address appears in the frame. Ethernet first transmits the least-significant bit of a data byte

on the wire. This makes the specific/group bit appear in bit 40 (least-significant bit of most-significant byte). For

example, a destination address of 0x12.34.56.78.9A. BC and a source address of 0xDE.F1.23.45.67.89 is seen

on the DD terminals as follows:

CYCLE

BIT

0x78

0x56

0x34

0x12

0xF1

0xDE

0xBC

0x9A

0x89

0x67

0x45

0x23

CRC checking and valid frames

The TNETX15VE determines the status of the frame when the end of buffer (EOB) followed by an end of frame

(EOF) is detected. CRC checking is determined from the frame-status field. The code for a good CRC is frame

status = 000b. All other frame-status codings indicate that the TNETX3150/TNETX3150A aborts the frame due

to either a CRC error, a FIFO overflow, or a network error. The frame status is checked when the option of adding

addresses to TNETX15VE tables on a good CRC is indicated rather than immediately.

operating logic arbitration

The lookup table is contained in both the external and internal SRAM. All of the TNETX15VE logic operations

share access to this SRAM. An arbitration scheme is implemented to give all logic operations fair access to the

SRAM while meeting the lookup-timing requirements.

The TNETX15VE contains seven logic operations that require the use of the SRAM bus. They are: the RAM

initialization logic operation (INIT), the lookup logic operation (LKUP), the delete logic operation (DEL), the add

logic operation (ADD), the management address-lookup logic operation (FIND), the RAM registers RAMaddr

and RAMdata (REG), and the aging logic operation (AGE).

The arbiter assigns a priority to each logic operation. The highest priority is assigned to the INIT logic operation

to initialize the TNETX15VE after a reset. After initialization, LKUP becomes the logic operation with the highest

priority. LKUP has the highest priority on the bus because it is the logic operation that is the most time critical.

The next priority level is shared by ADD and DEL. Register-based accesses (REG) are followed by the FIND

logic operation. AGE becomes the lowest priority. Figure 4 shows the priorities of the TNETX15VE logic

operations.

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