TNETX15VE datasheet(13/113 Pages) TI1

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TNETX15VE

VLAN-ENGINE ADDRESS-LOOKUP DEVICE

SPWS028B – APRIL 1997 – REVISED SEPTEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

general notation notes

Hexadecimal notation: Leading 0, followed by lower case x, then hex digits, with space or punctuation

delimiters on both ends. A...F are equivalent to a...f (example: 0x12bc, 0x12BC)

Binary notation:

Trailing lower-case b after string composed of only 1 or 0, with space or punctuation

delimiters on both ends (example: 101011b).

Decimal notation:

A number composed of 0...9 digits with no prefix or suffix, with a space or

punctuation delimiters on both ends (example: 23965)

The least-significant bit in a register is the lowest number.

The least-significant byte of a multibyte value is the lowest number.

node address format (Ethernet native data format)

The node addresses are kept inside TNETX15VE in Ethernet native data format. This is the same format used

when the address appears in the frame transmitted on the wire. Ethernet first transmits the least-significant bit

of a data byte on the wire. This makes the group/specific address appear in bit 40 (least-significant bit of

most-significant byte). TNETX15VE address storage format is shown in the following:

BIT

BYTE (most-significant byte)

BYTE

LOCAL/UNIVERSAL

ADDRESS

GROUP/SPECIFIC

ADDRESS

DIO register access

There are only four byte-wide DIO registers that are hardware interfaced to the DIO interface. These registers

are treated like a pointer structure to locate internal registers, some of which are interfaced to external terminals

of the device (see Figure 1). The small number of registers actually on the DIO interface give the TNETX15VE

a small I/O map requirement when designing systems; it also allows additional registers to be defined without

requiring the hardware interface to change.

To access an internal register, post both halves of the address to the DIO address-low and DIO address-high

registers and read or write the DIO data register. If the host performs a read, the internal state machine enables

the internal register at the posted address to drive the bus when the read cycle is active. If the host performs

a write to a TNETX15VE register, the value written to the data register address is transferred to the posted

address in the DIO address-low and DIO address-high registers. SRDY going low on a host read indicates that

the internal fetch was accomplished. A delay of up to 60 ns after cycle start is encountered if the resource being

requested is currently being used by an internal state machine. There are dedicated cycles for DIO to prevent

lockout, but they are allocated as 2 of 5, and DIO is asynchronous to internal processes. SRDY going low on

a host write indicates that the value written to the data register is captured and is written to the resource

addressed. For maximum throughput, SRDY should be part of the interface; if not, add 60 ns to the minimum

DIO cycle times.

If a range of consecutive (rising in order) accesses are needed, reading or writing to the DIO data auto-increment

Reads and writes can be mixed in a string of accesses; the post increment is by one after each cycle.

Since the DIO address high register is not likely to need the upper bits, one of them is overloaded; that is, it is

given a special use. A complete hardware reset is accomplished by writing 0x40 to the DIO address-high

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