TNETX15VE datasheet(73/113 Pages) TI1

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TNETX15VE

VLAN-ENGINE ADDRESS-LOOKUP DEVICE

SPWS028B – APRIL 1997 – REVISED SEPTEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

initialization

The TNETX15VE can be designed for stand-alone use, with no need for a management CPU. It can be reset

and initialized with or without a host CPU. This section deals with the steps necessary to bring the TNETX15VE

up to an operating level.

TNETX3150/TNETX3150A initialization

If multiple port EAM codings are used (forwarding to multiple ports), then TNETX3150/TNETX3150A IOBMOD

bit in the systcl register must be set to a 1. For proper operation, this TNETX3150/TNETX3150A setting must

be matched by setting NIOB in the TNETX15VE control register (0xA) to 0. If both bits are reversed (IOBMOD

in TNETX3150/TNETX3150A systcl register = 0, NIOB in TNETX15VE control register =1), the ability to send

frames to multiple ports, but not all ports, is lost. Multicasts become broadcasts to all ports, regardless of VLAN.

Also the broadcast is not in order with other traffic on each transmit queue. If both bits are set to 1 or 0,

unpredictable behavior results.

The user must also disable the TNETX3150/TNETX3150A internal address matching when using the

TNETX15VE. This is accomplished by writing a 1 to the ADRDIS bit in the port control register of each port. For

detailed information on the TNETX3150/TNETX3150A, the reader is referred to the TNETX3150/TNETX3150A

data sheet.

resetting the TNETX15VE

hardware reset

The TNETX15VE is hardware reset by asserting RESET low. The TNETX15VE comes out of reset when RESET

goes high. The TNETX15VE can also be hardware reset through the DIO interface by writing a 0x40 to the DIO

address high access register (DIO address low is a don’t care). Both actions are equivalent.

During a hardware reset, no access to the internal registers is allowed. A read or write stalls, that is, SRDY does

not go low until the hardware reset stimuli is removed. All access registers and internal registers are initialized

to default values.

If an EEPROM is detected (after a hardware reset), the TNETX15VE begins the EEPROM auto-loading

process. No DIO operations are allowed during auto-loading.

software reset

The TNETX15VE is software reset by setting the RESET bit to a 1 in the control register (0x08,0x09 DIO). The

TNETX15VE remains in the reset state until this bit is cleared. All internal registers are initialized to default

values during a software reset, except for the control register, which keeps its current value. Reading the internal

registers is allowed during a software reset, but the user is not able to write to any register (except for the control

The EEPROM auto-loading process does not start during a software reset. The user must assert the LOAD bit

in the control register for auto-loading to start.

TNETX15VE 数据表(PDF) 73 Page - Texas Instruments

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