TNETX15VE datasheet(98/113 Pages) TI1

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TNETX15VE

VLAN-ENGINE ADDRESS-LOOKUP DEVICE

SPWS028B – APRIL 1997 – REVISED SEPTEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

timing requirements (see Note 9 and Figure 23)

DIO write cycle

NO.

MIN

MAX

UNIT

tsu(SRNW)

Setup time, SRNW low before ESCS

↓

tsu(SAD)

Setup time, SAD1–SAD0 valid before ESCS

↓

tsu(SDATA)

Setup time, SDATA7–SDATA0 valid before ESCS

↓

NOTE 9: The DIO interface is a byte-wide, asynchronous interface that is designed for use with a wide variety of CPUs. The interface can be

run at any speed; there is no minimum speed requirement. DIO cycle lengths can vary, depending on the type of register accessed.

The TNETX15VE withholds the SRDY acknowledge signal on some registers until it has gathered the necessary data.

operating characteristics over recommended operating conditions (see Note 9 and Figure 23)

DIO write cycle

NO.

PARAMETER

MIN

MAX

UNIT

tw(SRDVH)

Pulse duration, SRDY high (see Note 11)

td(SRNW)

Delay time, from SRDY

↓ to SRNW↑

td(SAD)

Delay time, from SRDY

↓ to SAD1–SAD0 invalid

td(SDATA)

Delay time, from SRDY

↓ to SDATA7–SDATA0 high-impedance Z

td(SRDY)1

Delay time, from ESCS

↓ to SRDY↓ (see Note 10)

25+N(20)

td(SRDY)2

Delay time, from ESCS

↑ to SRDY↑ (see Note 11)

td(ESCS)

Delay time, from SRDY

↓ to ESCS↑

NOTES:

9. The DIO interface is a byte-wide, asynchronous interface that is designed for use with a wide variety of CPUs. The interface can

be run at any speed; there is no minimum speed requirement. DIO cycle lengths can vary, depending on the type of register

accessed. The TNETX15VE withholds the SRDY acknowledge signal on some registers until it has gathered the necessary data.

10. N equals the number of internal cycles required to arbitrate internally to obtain the value being requested. N is equal to a

minimum of 1, and can be quite large during RAM INIT and FINDNEXT operations. Since DIO operations are not complete during

these operations (no SRDY true), both of these operations can read every SRAM location to finish.

11. These numbers are specified by design but not tested.

Data

ESCS

(input)

SRNW

(input)

SDATA7–SDATA0

(input)

SRDY

(output)

Host Address

SAD1–SAD0

(input)

Data

Figure 23. DIO Write Cycle

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