TNETX15VE datasheet(65/113 Pages) TI1

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TNETX15VE

VLAN-ENGINE ADDRESS-LOOKUP DEVICE

SPWS028B – APRIL 1997 – REVISED SEPTEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

RAMsize and number of nodes supported

The address capability for the various RAM sizes is given in Table 4. The numbers are upwardly limited by the

table leaves that can be stored in the TNETX15VE 4K x 16 internal SRAM. The minimum size of external SRAM

that supports 1954 addresses (worst case) is 512K x 16 (RAMsize = 0x0B).

Table 4. Address Capability for RAM Sizes

RAMsize

RAM SIZE

WORST CASE

BEST CASE

0x00

640 x 16

0x01

832 x 16

136

0x02

1K x 16

184

0x03

2K x 16

432

0x04

4K x 16

920

0x05

8K x 16

1912

0x06

16K x 16

1954

0x07

32K x 16

123

1954

0x08

64K x 16

251

1954

0x09

128K x 16

507

1954

0x0A

256K x 16

1019

1954

0x0B

512K x 16

1954

0x0C

1M x 16

1954

0x0D–0x0F

Reserved

The data in Table 4 shows a large range between the worst-case performance and the best-case performance.

For a 500-address system, 128K x 16 is needed. A 1-K address system requires 256K x 16. A 2-K address

system requires 512K x 16. Adding more than 512K x 16 to the TNETX15VE does not increase the address

storage capacity since it exceeds the internal SRAM limit.

The difference between the two numbers at each row depends on the similarity (when viewed in 5-bit groups)

of the addresses entered into the table. If addresses are sequential, there is maximal table sharing, and the most

addresses fit into the smallest space. If addresses are widely spaced with respect to the 5-bit groups, there is

minimal table sharing, because each 32-entry table has only one entry at each level. This requires the most

SRAM per address.

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