TNETX15VE datasheet(90/113 Pages) TI1

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TNETX15VE

VLAN-ENGINE ADDRESS-LOOKUP DEVICE

SPWS028B – APRIL 1997 – REVISED SEPTEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

ADD interrupts (NEW, NEWM, CHNG, CHNGM, SECVIO, SECVIOM, and FULL)

The ADD interrupts generate collateral information in the following registers:

BYTE 3

BYTE 2

BYTE 1

BYTE 0

DIO ADDRESS

Newnode23–Newnode16

Newnode31–Newnode24

Newnode39–Newnode32

Newnode47–Newnode40

0x30

Newport

Newnode7–Newnode0

Newnode15–Newnode8

0x34

Add interrupts are sourced by the ADD logic operation only based on information from the wire. ADD indicates

a new address by a NEW interrupt, an address is changing ports by a CHNG interrupt, and a security violation

by a SECVIO interrupt.

The FULL interrupt indicates that ADD needed to start AGE (to free up table space) if NAUTO is 0, or the host

needs to delete some addresses if NAUTO = 1.

The add interrupts are indicated in the interrupt register and the information for the particular interrupt is placed

in the newnode and newport registers. Since there is only one set of registers that is shared for these interrupts

and to ensure that the information placed in these registers is not corrupted during reads, ADD locks the

newnode and newport registers until the most-significant byte of newport is read.

Locking these registers means that ADD does not have a place to put information for new events. If additional

events are missed, they are indicated in the int register as missed interrupts (NEWM, CHNGM, and SECVIOM).

On a NEW interrupt, the newport register contains information about the node’s VLAN and the port for the new

address. On a CHNG interrupt, this register identifies the new port address. On a SECVIO interrupt, the address

does not move to the port, but the newport register indicates to which port it tried to move.

aging interrupts (AGE, AGEM)

When an address is aged out by the internal AGE logic, it generates an interrupt and reports about that address

in the following registers:

BYTE 3

BYTE 2

BYTE 1

BYTE 0

DIO ADDRESS

Agednode23–Agednode16

Agednode31–Agednode24

Agednode39–Agednode32

Agednode47–Agednode40

0x40

AgedVLAN

Agedport

Agednode7–Agednode0

Agednode15–Agednode8

0x44

AGE indicates an interrupt every time that it ages out a node. It places the information on the node (being aged

out) on the agednode register, the node’s port on agedport, and VLAN in the agedVLAN register. These registers

are locked when a new interrupt is given to protect the information contained.

Missed interrupts due to these registers being locked are indicated as an AGEM interrupt. These registers are

unlocked when the agedVLAN register is read.

statistic interrupt (STAT)

The statistic interrupt is given when one of the statistic registers (except for numnodes) becomes one-half full;

the most-significant bit becomes a 1. This is an indication to the management CPU that the statistic registers

should be read to avoid counter overrun. Reading a statistic counter, except for numnodes, clears it.

FIND interrupt (FNDCPLT)

The FIND interrupts are implemented to indicate when the FIND logic operation has completed a FIND

command. The software either polls the FIND command bit for a complete indication or it is hardware interrupted

by setting the FNDCPLT bit in intmask. This bit is cleared when read.

NBLCK RX FIFO interrupt (RXFIFO)

The NBLCK RX FIFO interrupt is implemented to indicate when the NBLCK FIFO has information in it (not

empty). The source address, port, and tag information is placed on this FIFO when the destination address

matches an address in the lookup table that has the NBLCK bit set.

TNETX15VE 数据表(PDF) 90 Page - Texas Instruments

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