TNETX15VE datasheet(71/113 Pages) TI1

71 / 113 page

TNETX15VE

VLAN-ENGINE ADDRESS-LOOKUP DEVICE

SPWS028B – APRIL 1997 – REVISED SEPTEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

host (access) register space (continued)

Improvement on the preceding steps is obtained by writing a 0x00 to DIO address high and changing only DIO

address low. More steps can be eliminated by using the DIO data auto-increment register to read or write to

contiguous register bytes. The following shows how to use the auto-incrementing function to access the control

• Write a 0x00 to DIO address high

• Write a 0x08 to DIO address low to select DIO address 0x08

• Read the least-significant bit of the control register by reading DIO data auto-increment or write to the

least-significant bit of the control register by writing to DIO data auto-increment. The address in DIO

address auto-increments to 0x0009.

• Read the most-significant bit of the control register by reading DIO data auto-increment, or write to the

most-significant bit of the control register by writing to DIO data auto-increment.

The auto-incrementing function is useful when reading or writing to a large number of adjacent registers, such

as the 48-bit address registers or when reading the statistics block.

internal registers

The internal registers are used to initialize and/or software-reset the TNETX15VE, select the TNETX15VE

startup and routing options, checks the number of nodes within the TNETX15VE and statistics, enable

management-based operations on the lookup table, and interface with the on-chip or external SRAM, the

EEPROM, and any MII-managed devices.

The internal registers are described in the detailed

internal register section of this document. This section

provides additional information on the use of internal registers to access the SRAM, MII devices, and EEPROM.

lookup-table SRAM access

DIO ADDRESS

0x00

BYTE 3

BYTE 2

BYTE 1

BYTE 0

0x20

0x24

RAMsize

RAM addr

RAM data

The TNETX15VE SRAM (internal and external) can be accessed through the internal registers with the RAM

addr and RAM data registers. The algorithm for reading and writing to the RAM is similar to that for reading and

writing to the internal registers; the address of the location to access is placed in RAM addr and the data is read

from or written to RAM data.

To select between internal or external RAM, the RSEL bit in the RAM addr register is used. This interface also

has an auto-increment function, which is selected from the INC bit in RAM addr. The auto-incrementer

increments by one when the most-significant bit of RAM data is read or written to.

The DIO state machine must request access to SRAM via the SRAM bus scheduler. A write to SRAM is queued

when the most-significant byte of RAM data is written. A read of SRAM is queued when either byte of RAM data

is read through the DIO port.

TNETX15VE 数据表(PDF) 71 Page - Texas Instruments

TNETX15VE 数据表(HTML) 71 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载