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TNETX15VE

VLAN-ENGINE ADDRESS-LOOKUP DEVICE

SPWS028B – APRIL 1997 – REVISED SEPTEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

lookup algorithm (continued)

Table

2nd Level : 2N Tables

22N Threads

23N Tables

3rd Level :

23N Threads

Table

N = Number of Bits Compared

Figure 5. Lookup-Algorithm Table Hierarchy

The first level (root level) has only one table from which it can branch out to 2N possible tables. N is the number

of bits compared. Each additional table in the hierarchy branches down to 2N other possible tables. The second

level contains 2N table and 22N threads. The third level contains 22N tables and 23N threads, and so on.

Because of this exponential growth, the threads and the amount of possible paths at each level soon overtake

the number of addresses required. If this growth was unchecked with an N of 5, the third level would contain

1,024 tables and 32,768 threads. If only 1024 addresses are required, there are more tables allocated than

needed, and most contain NULL pointers.

For bit groups of five (give table sizes of 32), and with five levels of table hierarchy, preassigning all possible

tables at initialization requires more RAM than is possible to attach to the TNETX15VE. Therefore, table

allocation occurs only when a new table is required as a result of discovering a bit pattern at any of the levels

previously unseen. This has several side effects – given the same address set, entering them into the table in

a different order yields different SRAM contents; pointer values are written to the table entries to point to the

next level in the hierarchy since it is dynamically allocated. An address is in the table if there are valid entries

at each level in the hierarchy (as each n-bit part of the address is inspected) that continue all the way down to

a leaf where the characteristics of that address are stored. An address is not present in the table when there

is a 0 pointer at any level of the decode. Addresses that are sequential share all the intermediate pointers down

to the address of the leaf. Addresses with at least one bit different in each n-bit inspection unit occupy completely

different tables. The worst-case rating on the storage capacity of the TNETX15VE SRAM assumes that each

address is different from all the others by at least one bit in each inspection unit. This implies that each card is

from a different manufacturer, and no serial number of any card is within a table size of any other card.

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