TNETX15VE datasheet(48/113 Pages) TI1

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TNETX15VE

VLAN-ENGINE ADDRESS-LOOKUP DEVICE

SPWS028B – APRIL 1997 – REVISED SEPTEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

mirror port select register, mirrorport at 0xF2 (DIO)

BIT

Reserved

Mirrorport

Initial Values After Reset

The mirrorport register selects the TNETX3150/TNETX3150A port that is monitored when the MIRR bit in the

control register (0x8, 0x9) is on.

blocking registers

The blocking registers and the CPUTX register support the various states of the spanning-tree algorithm.

The TXblock register allows the host to stop packets from being queued for output (forwarded or transmitted)

on a port-by-port basis. Any port with its corresponding bit set does not have any frames added to its transmit

queue, except by the transmit-override mechanism. The CPUTX register is used to activate the

transmit-override mechanism. When the TX routing code is not 0xF, the next frame from the CPU port is queued

and transmitted on the TX routing code port, regardless of the state of the TXblock bit for that port. The CPU

port value specifies the source port of a specially treated packet, and the TX routing code value specifies the

destination port of a specially treated packet.

The RXblock register allows the host to not accept packets on a port-by-port basis. The bit numbers correspond

to the port being blocked. Packets that arrive from any station on a port with its corresponding bit set are ignored.

They are not counted in any of the statistics counters. This barrier is overridden on an address-by-address basis

by setting the NBLCK bit (bit 15 of the addport register) via an ADD/EDIT operation. Addresses with this bit set

are received normally.

Using the CPUTX register to queue a frame for transmission bypasses the normal TNETX15VE table lookup

on the destination address, and overrides the TXblock barrier to transmit. This mechanism can be used at any

time to steer one packet from the CPU port to the TX routing code port. The CPUTX register is reset to 0xF, a

nonfunctional value, after one packet is handled under its influence.

The CPUTX register is used to reply to received spanning-tree BPDU packets. The multicast address port vector

for BPDUs is set to point only to the port where the management entity was connected – this would ensure that

the BPDUs are sent to the right place. The NBFR bit (bit 5) of the findcontrol register (0x16) would be used to

discover the source port for each inbound BPDU. When the reply is composed, the CPUTX register is used to

steer the packet to the right port, past the TXblock barrier.

forwarding block register, TXblock at 0xF4–0xF5 (DIO)

BYTE 1

BYTE 0

BIT

Reserved

TXblock

Initial Values After Reset

The TXblock register blocks forwarding (transmitting) on ports that have their corresponding bit set. Packets

destined for ports that are forwarding blocked are discarded. The TXblock register can be overridden on one

frame at a time using the CPUTX registers.

TNETX15VE 数据表(PDF) 48 Page - Texas Instruments

TNETX15VE 数据表(HTML) 48 Page - Texas Instruments

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