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TNETX15VE 数据表(PDF) 99 Page - Texas Instruments |
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TNETX15VE 数据表(HTML) 99 Page - Texas Instruments |
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99 / 113 page  TNETX15VE VLAN-ENGINE ADDRESS-LOOKUP DEVICE SPWS028B – APRIL 1997 – REVISED SEPTEMBER 1997 99 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 When the host is driving the EEPROM interface through the SIO register (0x0A0), the output terminals are copies of register bits synchronized by OSCIN rising, and the input register bits are copies of the device terminals synchronized by OSCIN rising. This adds a maximum of 20 ns of delay in each direction, which is negligible in terms of the maximum signal change rate allowed for the EEPROMs (approximately 100 kHz), or the MDIO (MII management). The timing for these interfaces is set at the rate that register bits are set in software. For detailed descriptions of the EEPROM requirements, the reader is referred to the data sheet for the part in question. For detailed descriptions of the MII management interface, the reader is referred to the IEEE Std 802.3 specification. When the TNETX15VE is driving the EEPROM during the automatic register load cycle, the timing on the EEPROM is shown in Figure 24. operating characteristics over recommended operating conditions (see Note 12 and Figure 24) EEPROM interface timing NO. PARAMETER MIN MAX UNIT fclock Clock frequency, ECLK 98 kHz 1 td(EDIO)1 Delay time, from ECLK ↑ to EDIO↓ 5 µs 2 td(ECLK)1 Delay time, from EDIO ↓ to ECLK↓ 5 µs 3 td(EDIO)2 Delay time, from ECLK ↓ to EDIO invalid 0 µs 4 td(ECLK)2 Delay time, from EDIO valid to ECLK ↑ 10 ns 5 td(EDIO)3 Delay time, from ECLK ↓ to EDIO valid 0 µs 6 td(EDIO)4 Delay time, from ECLK ↓ to EDIO invalid 0 µs 7 td(EDIO)5 Delay time, from ECLK ↑ to EDIO↑ 5 µs NOTE 12: The following timing refers to the waveforms that the TNETX15VE logic operation outputs while in operation. The EEPROM interface also can be accessed through the SIO register. When accessing the EEPROM through SIO, it is the user’s responsibility to ensure proper timing. Proper timing is ensured through software by toggling the appropriate SIO bits at the appropriate time. 7 ECLK (output) EDIO (output) EDIO (input) 1 2 5 6 3 4 Valid Valid Figure 24. EEPROM Interface Timing |
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