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TNETX15VE 数据表(PDF) 34 Page - Texas Instruments |
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TNETX15VE 数据表(HTML) 34 Page - Texas Instruments |
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34 / 113 page  TNETX15VE VLAN-ENGINE ADDRESS-LOOKUP DEVICE SPWS028B – APRIL 1997 – REVISED SEPTEMBER 1997 34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 interrupt masking register, intmask at 0x2A–0x2B (DIO) The intmask register is used with the int register to select the type of interrupts that should be given to the attached CPU. Bit definitions in the intmask register agree one-to-one to the bit definitions in the int register. Only those fields with the bit set to 1 generate an interrupt to the CPU. Setting the mask bit for a condition prevents only the external terminal from moving to a logic 1 when the appropriate condition is true. The appropriate bit in the interrupt register is always a 1 if the condition is true, and the bit has not been cleared by being read. This register is read/writeable. BYTE 3 BYTE 2 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NEW NEWM CHNG CHNGM SECVIO SECVIOM AGE AGEM INT FNDCPLT Reserved RXFIFO STAT FULL Initial Values After Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NAME FUNCTION 15 NEW New-node interrupt mask. When NEW is set, a new-node interrupt is posted if the NEW bit in the int register is set. 14 NEWM Missed-new-node interrupt mask. When NEWM is set, a missed new-node interrupt is posted if the NEWM bit in the int register is set. 13 CHNG Node-port change interrupt mask. When CHNG is set, a node-port change interrupt is posted if the CHNG bit in the int register is set. 12 CHNGM Missed-node-port change interrupt mask. When CHNGM is set, a missed-node-port interrupt is posted if the CHNGM bit in the int register is set. 11 SECVIO Security-violation interrupt mask. When SECVIO is set, a security-violation interrupt is posted if the SECVIO bit in the int register is set. 10 SECVIOM Missed-security-violation interrupt mask. When SECVIOM is set, a missed-security-violation interrupt is posted if the SECVIOM bit in the int register is set. 9 AGE Age-out interrupt mask. When AGE is set, an age-out interrupt is posted if the AGE bit in the int register is set. 8 AGEM Missed-age-out interrupt mask. When AGEM is set, a missed age-out interrupt is posted if the AGEM bit in the int register is set. 7 INT Test interrupt mask. When INT is set, a test interrupt is posted if the INT bit in the int register is set. 6 FNDCPLT Find completion mask. When FNDCPLT is set, a find completion interrupt is posted if the FINDCPLT bit in the int register is set. 5–3 Reserved Writes to this location are ignored and read as 0. 2 RXFIFO Receive FIFO not empty. When RXFIFO is set to 1, the receive frame address buffer is not empty. During spanning tree, this signals the arrival of a BPDU. 1 STAT Statistics overflow interrupt mask. When STAT is set, a statistics interrupt is posted if the STATS bit in the int register is set. 0 FULL SRAM full interrupt mask. When FULL is set, a memory-full interrupt is posted if the FULL bit in the int register is set. |
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