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TNETX15VE 数据表(PDF) 97 Page - Texas Instruments |
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TNETX15VE 数据表(HTML) 97 Page - Texas Instruments |
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97 / 113 page  TNETX15VE VLAN-ENGINE ADDRESS-LOOKUP DEVICE SPWS028B – APRIL 1997 – REVISED SEPTEMBER 1997 97 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements (see Note 9 and Figure 22) DIO read cycle NO. MIN MAX UNIT 1 tsu(SRNW) Setup time, SRNW high before ESCS ↓ 4 ns 2 tsu(SAD) Setup time, SAD1–SAD0 valid before ESCS ↓ 4 ns NOTE 9: The DIO interface is a byte-wide, asynchronous interface that is designed for use with a wide variety of CPUs. The interface can be run at any speed; there is no minimum speed requirement. DIO cycle lengths can vary, depending on the type of register accessed. The TNETX15VE withholds the SRDY acknowledge signal on some registers until it has gathered the necessary data. operating characteristics over recommended operating conditions (see Note 9 and Figure 22) DIO read cycle NO. PARAMETER MIN MAX UNIT 3 tw(SRDYH) Pulse duration, SRDY high (see Note 11) 25 ns 4 td(SRNW) Delay time, from SRDY ↓ to SRNW↓ 0 ns 5 td(SAD) Delay time, from SRDY ↓ to SAD1–SAD0 invalid 0 ns 6 td(SDATA)1 Delay time, from SDATA7–SDATA0 valid to SRDY ↓ –7 ns 7 td(SDATA)2 Delay time, from ESCS ↑ to SDATA7–SDATA0 high-impedance Z 17 ns 8 td(SRDY)1 Delay time, from ESCS ↓ to SRDY↓ (see Note 10) 25+N(20) ns 9 td(SRDY)2 Delay time, from ESCS ↑ to SRDY↑ (see Note 11) 25 ns 10 td(ESCS) Delay time, from SRDY ↓ to ESCS↑ 0 ns NOTES: 9. The DIO interface is a byte-wide, asynchronous interface that is designed for use with a wide variety of CPUs. The interface can be run at any speed; there is no minimum speed requirement. DIO cycle lengths can vary, depending on the type of register accessed. The TNETX15VE withholds the SRDY acknowledge signal on some registers until it has gathered the necessary data. 10. N equals the number of internal cycles required to arbitrate internally to obtain the value being requested. N is equal to a minimum of 1, and can be large during RAM INIT and FINDNEXT operations. Since DIO operations are not complete during these operations (no SRDY true), both of these operations can read every SRAM location to finish. 11. These numbers are specified by design but not tested. ESCS (input) SRNW (input) SDATA7– SDATA0 (output) SRDY (output) Z Z 1 7 Host Address 3 8 9 5 4 6 2 SAD1–SAD0 (input) Data 10 Figure 22. DIO Read Cycle |
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