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TNETX15VE 数据表(PDF) 100 Page - Texas Instruments |
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TNETX15VE 数据表(HTML) 100 Page - Texas Instruments |
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100 / 113 page  TNETX15VE VLAN-ENGINE ADDRESS-LOOKUP DEVICE SPWS028B – APRIL 1997 – REVISED SEPTEMBER 1997 100 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements OSCIN clock MIN NOM MAX UNIT tc(OSCIN) Cycle time, OSCIN 20 20 ns tw(OSCINH) Pulse duration, OSCIN high 8 10 ns tw(OSCINL) Pulse duration, OSCIN low 8 10 ns Frequency drift, OSCIN clock ±50 ppm timing requirements (see Figure 25) power-on reset NO. MIN MAX UNIT 1 td(RESET)1 Delay time, from VCC↑ to RESET↑ 25 ms 2 td(RESET)2 Delay time, from OSCIN ↑ to RESET↑ 25 ms 3 td(AUTO) Delay time, from RESET ↑ to EEPROM autoload finished 50 ms OSCIN (input) VCC(5V) (input) VCC (input) 1 2 RESET (input) Normal Operation Signals† Valid † Outputs are floated during reset. Inputs and I/O’s that are not connected to a known logic state at all times, including reset, should have a pullup or pulldown resistor. 3 Figure 25. Power-On Reset Timing |
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