TNETX15VE datasheet(72/113 Pages) TI1

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TNETX15VE

VLAN-ENGINE ADDRESS-LOOKUP DEVICE

SPWS028B – APRIL 1997 – REVISED SEPTEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

serial interface – MII-managed devices

BYTE 3

BYTE 2

BYTE 1

BYTE 0

DIO ADDRESS

SIO

0x08

The TNETX15VE gives the programmer an easy way to implement a software-controlled bit-serial interface.

This interface is most appropriate in implementing a media-independent interface (MII) management serial

interface.

MII devices, which implement the management interface consisting of MDIO and MDCLK, are accessed in this

way though the SIO register. In addition (for PHYs that support this) the TNETX15VE implements a third

MII-management signal, MRESET, to hardware-reset MII PHYs.

MDIO requires an external pullup for operation. The I/O direction is controlled by the MTXEN bit, and the

external terminal state is set from or read in MDATA. The complete serial interface (MDIO, MDCLK, MRESET)

can be placed in a high-Z state through the MDIOEN bit in SIO. High-Z support is needed to prevent two or more

devices from driving the MII bus at the same time.

The TNETX15VE does not implement any timing or data structure on its serial interface. Appropriate timing and

frame format must be assured by the management software by setting or clearing bits at the right time and in

the right order. Refer to the IEEE Std 802.3u specification and the data sheet for the MII-managed device for

the nature and timing of the MII waveforms.

x24C02 EEPROM interface

BYTE 3

BYTE 2

BYTE 1

BYTE 0

DIO ADDRESS

SIO

Control

0x08

The flash EEPROM interface is provided so the system-level manufacturers can provide an optional configured

system to their customers. Customers can change or reconfigure the system and retain preferences between

system power downs. The flash EEPROM contains configuration and initialization information that is accessed

infrequently (typically at power up and reset). The host can write to the EEPROM through this SIO register

interface.

The TNETX15VE implements a two-wire serial interface, consisting of EDIO and EDCLK that communicates

with the EEPROM. Similar to the MII interface, the TNETX15VE does not implement any timing or data structure

on its serial interface. Appropriate timing and frame format must be ensured by the management software by

setting or clearing bits at the right times. There are no limits to the size or organization of the EEPROM when

the host is driving this interface, but these same terminals are used by an internal state machine to load the

contents of the EEPROM into internal registers. This state machine expects a 24C02 (as device 0) on the serial

bus. Refer to the manufacturer’s data sheet for a description of the EEPROM waveforms.

If an EEPROM is not installed, EDIO should be tied low. For EEPROM operation, EDIO and EDCLK require an

external pullup (see EEPROM data sheet). TNETX15VE detects the presence or absence of the EEPROM and

indicates this in the NEEPM bit of the control register.

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