 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
TNETX15VE 数据表(PDF) 89 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
TNETX15VE 数据表(HTML) 89 Page - Texas Instruments |
|
|
89 / 113 page  TNETX15VE VLAN-ENGINE ADDRESS-LOOKUP DEVICE SPWS028B – APRIL 1997 – REVISED SEPTEMBER 1997 89 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PRINCIPLES OF OPERATION masking interrupts The programmer may be interested in processing some interrupts now, while leaving the others for a later time. The TNETX15VE can mask interrupts. This is accomplished by an interrupt masking register, (intmask). The int and intmask registers have a one-to-one correspondence. The only way EINT is asserted is if both int and intmask are in a 1 state. The logic for the interrupt masking is shown in Figure 17. Int Register Intmask Register AND AND OR EINT Interrupt Mask Register Interrupt Register Figure 17. Interrupt Masking Logic test interrupts (INT) Test interrupts are generated by asserting the INT bit in the int register. The INT bit in the intmask register must also be set to a 1 state for the interrupt to take effect. The INT bit is used to give the programmer an easy way to test interrupt detection. This bit is the only bit in the int register that is writeable. |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
