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TNETX15VE 数据表(PDF) 94 Page - Texas Instruments |
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TNETX15VE 数据表(HTML) 94 Page - Texas Instruments |
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94 / 113 page  TNETX15VE VLAN-ENGINE ADDRESS-LOOKUP DEVICE SPWS028B – APRIL 1997 – REVISED SEPTEMBER 1997 94 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements (see Figure 19) external SRAM write cycle NO. MIN MAX UNIT 1 tc(W) Cycle time, write 40 ns operating characteristics over recommended operating conditions (see Figure 19) external SRAM write cycle NO. PARAMETER MIN MAX UNIT 2 td(EA) Delay time, from OSCIN ↑ to EA20–EA0 valid 16 ns 3 td(EWE)1 Delay time, from OSCIN ↓ to EWE↓ 14 ns 4 td(ED)1 Delay time, from OSCIN ↓ to ED15–ED0 valid 14 ns 5 td(EWE)2 Delay time, from OSCIN ↑ to EWE↑ 2 12 ns 6 td(ED)2 Delay time, from EWE ↑ to ED15–ED0 invalid 0 10 ns 7 td(EA)2 Delay time, from EWE ↑ to EA20–EA0 transition (change) 0 ns 8 td(ED)3 Delay time, from OSCIN ↑ to ED15–ED0 high-impedance Z 16 ns Z 4 1 5 Z 6 EA20–EA0 (output) EWE (output) EOE (output) ED15–ED0 (output) OSCIN (input) Valid 2 Valid Valid 3 8 7 2 Figure 19. External SRAM Write Cycle |
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