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TNETX15VE 数据表(PDF) 96 Page - Texas Instruments

部件名 TNETX15VE
功能描述  VLAN-ENGINE ADDRESS-LOOKUP DEVICE
PDF  113 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

TNETX15VE 数据表(HTML) 96 Page - Texas Instruments

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TNETX15VE
VLAN-ENGINE ADDRESS-LOOKUP DEVICE
SPWS028B – APRIL 1997 – REVISED SEPTEMBER 1997
96
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
timing requirements (see Note 8 and Figure 21)
DRAM interface
NO.
MIN
MAX
UNIT
1
tsu(DD)
Setup time, DD35–DD0 valid before OSCIN
↑
12
ns
2
tsu(DWE)
Setup time, from DWE
↓ to OSCIN↑
4
ns
3
tsu(DRAS)
Setup time, from DRAS
↓ to OSCIN↑
4
ns
4
tsu(DCAS)
Setup time, from DCAS
↓ to OSCIN↑
4
ns
5
th(DD)
Hold time, DD35–DD0 valid after OSCIN
↑
3
ns
6
th(DWE)
Hold time, DWE low after OSCIN
↑
3
ns
7
th(DRAS)
Hold time, DRAS low after OSCIN
↑
3
ns
8
th(DCAS)
Hold time, DCAS low after OSCIN
↑
3
ns
NOTE 8: The TNETX15VE monitors the DRAM interface to extract frame information. The TNETX15VE extracts information on only the write
cycles. The TNETX15VE does not output any signals to the DRAM interface. The only parameters that apply to the TNETX15VE on
this interface are delay times, with respect to OSCIN, that translate into the TNETX15VE setup times. The TNETX15VE implements
internal delay elements to ensure its setup requirements.
OSCIN
(input)
Data
DWE
(input)
DRAS
(input)
DCAS
(input)
DD35–DD0
(input)
1
4
2
Z
Z
TNETX15VE Latches Here
3
5
6
7
8
Figure 21. DRAM Interface Timing



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