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TNETX15VE 数据表(PDF) 104 Page - Texas Instruments |
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TNETX15VE 数据表(HTML) 104 Page - Texas Instruments |
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104 / 113 page  TNETX15VE VLAN-ENGINE ADDRESS-LOOKUP DEVICE SPWS028B – APRIL 1997 – REVISED SEPTEMBER 1997 104 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 APPLICATION INFORMATION TNETX15VE and TNETX3150/TNETX3150A stand-alone applications (continued) In-band signaling (see Figure 29) must be done with a MAC device connected to one of the switch ports. There is no access to the data stream via the DIO port on the TNETX3150/TNETX3150A or the TNETX15VE. Both devices affect the ability of a port to receive or forward packets; the packet itself is received and transmitted via a regular switch port. With access to a port, the CPU can receive frames destined to other nodes. By tagging the CUPLNK bit for that particular address in the address table, the CUPLNK bit copies all frames destined for that address to the ports specified in UPLINKport. By setting UPLINKport to direct these frames to the management CPU, it can receive frames of interest. CPU Manager SRAM EEPROM TNETX15VE TNETX3150/ TNETX3150A DIO OSC PHY PHY EEPROM Multiports MII MAC Figure 29. In-Band Managed Multiport Switch expansion through uplink The TNETX15VE includes functionality to enable two TNETX3150/TNETX3150As to be cascaded through their port 00. This is accomplished through the TNETX15VE pretag support. The outbound pretag carries port number information, which can be decoded by the inbound TNETX15VE into VLANIDs. The TNETX15VE works in a cascaded system as either a managed or unmanaged device. Figure 30 shows this application. The host processor needs access to the DIO bus of both device sets and needs to coordinate VLAN assignments across both address-lookup tables. TNETX15VE No. 1 TNETX3150/ TNETX3150A No. 1 PHY PHY PHY Multiports TNETX3150/ TNETX3150A No. 2 PHY PHY PHY Multiports TNETX15VE No. 2 Uplink Port 00 Figure 30. Cascaded Switches Through Uplink With Pretag Support |
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