RM0319 datasheet(354/368 Pages) STMICROELECTRONICS

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DMA controller (DMAC)

RM0319

354/368

Doc ID 022640 Rev 3

Note:

The DMAC uses HSIZE1 or HSIZE2 to indicate the width of a transfer, and if this fails to

match the width expected by the peripheral, then the peripheral can assert an error on

HRESP1

or HRESP2, respectively.

36.3.4

DMA interface

The DMA interface provides the set of signals (listed in Table 124) to be used by a generic

peripheral. Over this interface the connected peripheral is allowed to request a data transfer

(through DMA request signals), and DMA is able to reply to peripheral both acknowledging

the request and stating whether the data transfer has been completed (through DMA

response signals).

Each DMA request/response signal is 16-bit wide, allowing then DMAC connectivity with up

to 16 peripherals.

Note:

Some peripherals do not use all the signals provided by the DMA interface. In this case,

response signals that are not required can be left unconnected, and request signals that are

not required can be tied to low.

Because of DMA interface, the DMAC enables four different data transfer types:

●

Memory-to-memory

●

Memory-to-peripheral

●

Peripheral-to-memory

●

Peripheral-to-peripheral,

where each transfer can have either the peripheral or the DMAC as the flow controller,

resulting then in eight different scenarios (see FlowCntrl field in DMAC configuration

36.3.5

Scatter/gather

As mentioned before, the DMAC provides for scatter/gather DMA through the use of a series

of linked lists, allowing then source and destination of any DMA transfer to occupy non-

contiguous areas in memory.

Each item of a linked list, referred to as Linked List Item (LLI), controls the transfer of one

block of data (the packet) over a DMA channel, and then optionally loads another LLI to

continue the DMA operation (in case of more than a packet transfer), or stops the DMA

stream.

An LLI consists of four words:

●

the source address of the data to be transferred over a DMA channel,

●

the destination address of the data to be transferred over a DMA channel,

●

the pointer to next LLI (set to 0 in case current LLI is the last in its linked list),

●

a control word containing information about the corresponding DMA channel.

The first LLI of each linked list is programmed into the DMAC using the DMA channel

registers, namely DMACCnSrcAddr, DMACCnDestAddr, DMACCnLLI and DMACCnControl.

Then, these registers are updated as soon as a complete packet has been transferred over

the DMA channel by following the linked list.

Note:

The DMAC configuration is not part of the LLI description, but allows to configure the

relevant DMA channel.

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