RM0319 datasheet(356/368 Pages) STMICROELECTRONICS

356 / 368 page

DMA controller (DMAC)

RM0319

356/368

Doc ID 022640 Rev 3

36.4.1

How to operate single combined DMACINTR interrupt request signal

Wait until the combined interrupt request from the DMAC (DMACINTR) goes active.

Read the interrupt controller status register and determine whether the source of the

request was the DMAC.

Read the DMACIntStatus register to determine the DMA channel that generated the

interrupt. If more than one request is active (that is, more than one bit are set in the

IntStatus field), it is recommended to check the highest priority channels first (0, 1, 2

and so on).

Read the DMACIntTCStatus register to determine whether the interrupt was generated

because of the end of the transfer or because an error occurred. If the bit

corresponding to the DMA channel (from step #3) in the field IntTCStatus is set, the

data transfer has been completed

› step #6.

Read the DMACIntErrStatus register to determine whether the interrupt was generated

because of the end of the transfer or because an error occurred. If the bit

corresponding to the DMA channel (from step #3) in the field IntErrorStatus is set, an

error occurred

› step #6

Set the relevant bit in the DMACIntTCClear register or in the DMACIntErrClr register,

respectively, to clear the interrupt request.

RM0319 数据表(PDF) 356 Page - STMicroelectronics