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3.0 System Wake-Up Control (SWC) (Continued)

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Conﬁguration Options

The SBGPIO Pin Configuration register controls the following basic configuration options:

• Pin Direction - Controlled by Output Enable (bit 0)

• Output Type - Push-pull vs. open-drain. It is controlled by Output Type (bit 1) by enabling/disabling the pull-up portion of

the output buffer.

• Weak Static Pull-up - May be added to any type of port (input, open-drain or totem pole). It is controlled by Pull-Up Control

(bit 2).

• Pin Lock - A GPIO pin may be locked to prevent any changes in the output value and/or the output characteristics. The

lock is controlled by Lock (bit 3). It disables writes to the SBGPDO register bits, and to bits 0-3 of the Standby GPIO Pin

Configuration register (Including the Lock bit itself). Once locked, it can be released by hardware reset only.

Operation

The value that is written to the SBGPDO register is driven to the pin, if the output is enabled. Reading from the SBGPDO

register returns its contents, regardless of the pin value or the port configuration. The SBGPDI register is a read-only register.

Reading from the SBGPDI register returns the pin value, regardless of what is driving it (the port itself, configured as an

output port, or the external device when the port is configured as an input port). Writing to this register is ignored.

Activation of the SBGPIO port is controlled by the same external, device-specific configuration bit (or a combination of bits)

that control the activation of the SWC. When the SWC logical device is inactive, access to both the SBGPDI and SBGPDO

registers is disabled. However, there is no change in the port configuration and in the SBGPDO value, and hence there is

no effect on the outputs of the pins.

Event Detection

The enhanced SBGPIO port supports input event detection. This functionality is based on three configuration bits. The con-

figuration and operation of the event detection capability is shown in Figure 12. An SWC status register reflects the status

of each input event. SWC configuration registers determine the effect of each input event on the various means of system

notification available in the SWC.

Figure 12. Event Detection

Event

Enable

Event Polarity

Detected

Enabled Events

SBGPIO Pins

Input

Debouncer

Event

Internal

Bus

Level =1

R/W 1 to Clear

Status

Rising Edge or

Rising

Edge

Detector

from other

High Level =1

SBGPIO Pin Conﬁguration Register

Event Type

Event

Debounce

Enable

R/W

Bit 6

Bit 5

Bit 4

Indicator

Pending

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