PC87366 datasheet(125/240 Pages) NSC

部件名	PC87366

功能描述	128-Pin LPC SuperI/O with System Hardware Monitoring, MIDI and Game Ports

PDF	240 Pages

Scroll/Zoom	100%

制造商	NSC [National Semiconductor (TI)]

网页	http://www.national.com

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4.0 Fan Speed Control (Continued)

125

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4.3.3

Fan Speed Control Duty Cycle Register (FCDCR)

Location:

Device specific

Type:

R/W

4.4

FAN SPEED CONTROL BITMAP

Bit

76543210

Name

Duty Cycle Value

Reset

11111111

Bit

Description

7-0

Duty Cycle. The binary value of this 8-bit ﬁeld determines the number of clock cycles, out of a 256-cycle period,

during which the PWM output is high (while FANOUT is either equal to or the inverse of the PWM output,

depending on the Inverse FANOUT conﬁguration bit).

00h: PWM output is continuously low

01h - FEh: PWM output is high for [Duty Cycle Value] clock cycles and low for [256-Duty Cycle Value] clock

cycles

FFh: PWM output is continuously high

Bits

Offset

Mnemonic

76543210

Device

specific

Note 1.

Note 1. The location of this register is deﬁned in the

Device Architecture and Conﬁguration chapter.

FCPSR

Clock

Select

Pre-Scale Value

Device

specific

Note 1.

FCDCR

Duty Cycle Value

PC87366 数据表(PDF) 125 Page - National Semiconductor (TI)

PC87366 数据表(HTML) 125 Page - National Semiconductor (TI)

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