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数据搜索系统，热门电子元器件搜索 |
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PC87366 数据表(PDF) 129 Page - National Semiconductor (TI) |
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PC87366 数据表(HTML) 129 Page - National Semiconductor (TI) |
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129 / 240 page  5.0 Fan Speed Monitor (Continued) 129 www.national.com 5.4 FAN SPEED MONITOR BITMAP Bit Type Description 7 Reserved 6-5 R/W Clock Select. Selects the clock source provided to the counter. These bits must not be changed when the corresponding Fan Monitor Enable bit is 1 (enabled). 00: 16 KHz 01: 8 KHz (default) 10: 4 KHz 11: 2 KHz 4 R/W Filter Disable. When this bit is set to 1, the digital filter is disabled. When it is cleared, the filter is enabled. This bit should not be changed when the corresponding Fan Monitor Enable bit is 1 (enabled) to avoid unpredictable results. 0: Digital filter enabled (default) 1: Digital filter disabled 3 R/W Interrupt Enable. This bit controls the assertion of overflow interrupt and Over Threshold interrupt. 0: Interrupt disabled (default) 1: Interrupt enabled. Interrupt is asserted when an Over Threshold bit, Overflow bit or both are set to 1. 2 R/W1C Overflow. Indicates that the counter has passed FFh, and the fan speed is inefficiently slow; i.e., slower than 60 ∗ f/(256 ∗ n). Writing 1 to this bit clears it to 0. 0: No overflow occurred since the last time this bit was cleared (by reset or by writing 1) 1: Counter passed FFh 1 R/W1C Over Threshold. Indicates that the value loaded into the FMSPR register upon detection of the rising edge of the FANIN pulse exceeded the threshold value. 0: FMSPR register value did not exceed the threshold since the last time this bit was cleared (by reset or by writing 1) 1: FMSPR register value exceeded the threshold 0RO Speed Ready. This bit indicates that the speed register holds new (not yet read) and valid data. It is set to 1 on each rising edge of the FANIN input (starting from the second one) if the Over Threshold bit is 0. It is cleared to 0 whenever the speed register is read, or when the Overflow bit is set. 0: No new valid data in the FMSPR register (data is either invalid or has already been read) 1: FMSPR register loaded with new and valid data Register Bits Offset Mnemonic 7 6 5 43210 Device specific Note 1. Note 1. The location of this register is defined in the Device Architecture and Configuration chapter. FMTHR Threshold Value Device specific Note 1. FMSPR Fan Speed Reading Device specific Note 1. FMCSR Reserved Clock Select Filter Disable Interrupt Enable Overflow Over Threshold Speed Ready |
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