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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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PC87366 数据表(PDF) 135 Page - National Semiconductor (TI) |
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PC87366 数据表(HTML) 135 Page - National Semiconductor (TI) |
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135 / 240 page  6.0 General-Purpose Input/Output (GPIO) Port (Continued) 135 www.national.com 6.4.2 GPIO Pin Event Routing (GPEVR) Register This is a group of eight identical configuration registers, each of which is associated with one GPIO pin. The entire set is mapped to the PnP configuration space. The mapping scheme is based on the GPSEL register that functions as an index register, and the specific GPER register that reflects the routing configuration of the currently selected pin. For details on the GPSEL register, refer to the Device Architecture and Configuration chapter. This set of registers is applicable only for the enhanced GPIO port with event detection support. In the basic port this register set is reserved, returns 0 on read and has no effect on port functionality. Location: Device specific Type: R/W 6.4.3 GPIO Port Runtime Register Map Bit 76543210 Name Reserved GPIO Event to PWUREQ Enable GPIO Event to SMI Enable GPIO Event to IRQ Enable Reset 00000001 Bit Description 7-3 Reserved 2 GPIO Event to PWUREQ Enable. This bit is used to enable/disable the routing of the corresponding GPIO detected event to PWUREQ. 0: Disabled (default) 1: Enabled 1 GPIO Event to SMI Enable. This bit is used to enable/disable the routing of the corresponding GPIO detected event to SMI. 0: Disabled (default) 1: Enabled 0 GPIO Event to IRQ Enable. This bit is used to enable/disable the routing of the corresponding GPIO detected event to IRQ. 0: Disabled 1: Enabled (default) Offset Mnemonic Register Name Type Section Device specific Note 1. Note 1. The location of this register is defined in the Device Architecture and Configuration chapter in Section 2.15.1. GPDO GPIO Data Out R/W 6.4.4 Device specific Note 1. GPDI GPIO Data In RO 6.4.5 Device specific Note 1. GPEVEN GPIO Event Enable R/W 6.4.6 Device specific Note 1. GPEVST GPIO Event Status R/W1C 6.4.7 |
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