PC87366 datasheet(149/240 Pages) NSC

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8.0 ACCESS.bus Interface (ACB) (Continued)

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8.3.3

ACB Status Register (ACBST)

This register maintains the current ACB status. On reset, and when the ACB is disabled, ACBST is cleared (00h).

Location:

Offset 01h

Type:

Varies per bit

Bit

76543210

Name

SLVSTP

SDAST

BER

NEGACK

STASTR

NMATCH

MASTER

XMIT

Reset

00000000

Bit

Type

Description

R/W1C SLVSTP (Slave Stop). Writing 0 to SLVSTP is ignored.

0: Writing 1 or ACB disabled

1: Stop Condition detected after a slave transfer in which MATCH or GCMATCH was set

6RO

SDAST (SDA Status)

0: Reading from the ACBSDA register during a receive, or when writing to it during a transmit. When

ACBCTL1.START is set, reading the ACBSDA register does not clear SDAST. This enables ACB to

send a repeated start in master receive mode.

1: SDA Data register awaiting data (transmit - master or slave) or holds data that should be read

(receive - master or slave).

R/W1C BER (Bus Error). Writing 0 to BER is ignored.

0: Writing 1 or ACB disabled

1: Start or Stop Condition detected during data transfer (i.e., Start or Stop Condition during the transfer

of bits 2 through 8 and acknowledge cycle), or when an arbitration problem is detected.

R/W1C NEGACK (Negative Acknowledge). Writing 0 to NEGACK is ignored.

0: Writing 1 or ACB disabled

1: Transmission not acknowledged on the ninth clock (In this case, SDAST is not set)

R/W1C STASTR (Stall After Start). Writing 0 to STASTR is ignored.

0: Writing 1 or ACB disabled

1: Address sent successfully (i.e., a Start Condition sent without a bus error, or Negative Acknowledge),

if ACBCTL1.STASTRE is set. This bit is ignored in slave mode. When STASTR is set, it stalls the

ACCESS.bus by pulling down the SCL line, and suspends any further action on the bus (e.g., receive

of ﬁrst byte in master receive mode). In addition, if ACBCTL1.INTEN is set, it also causes the ACB

to send an interrupt.

R/W1C NMATCH (New Match). Writing 0 to NMATCH is ignored. If ACBCTL1.INTEN is set, an interrupt is sent

when this bit is set.

0: Software writes 1 to this bit

1: Address byte follows a Start Condition or a repeated start, causing a match or a global-call match.

1RO

Master

0: Arbitration loss (BER is set) or recognition of a Stop Condition

1: Bus master request succeeded and master mode active

0RO

XMIT (Transmit). Direction bit.

0: Master/slave transmit mode not active

1: Master/slave transmit mode active

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