PC87366 datasheet(146/240 Pages) NSC

146 / 240 page

8.0 ACCESS.bus Interface (ACB) (Continued)

146

www.national.com

Master Receive

After becoming the bus master, the device can start receiving data on the ACCESS.bus.

To receive a byte in an interrupt or polling operation, the software should:

1. Check that the SDAST bit of the ACBST register is set and that the BER bit is cleared. If the STASTRE bit of the

ACBCTL1 register is set, also check that the STASTRE bit of the ACBST register is cleared (and clear it if required).

2. Set the ACK bit of the ACBCTL1 register to 1, if the next byte is the last byte that should be read. This causes a negative

acknowledge to be sent.

3. Read the data byte from the ACBSDA register.

Before receiving the last byte of data, set the ACK bit of the ACBCTL1 register.

Master Stop

To end a transaction, set the STOP bit of the ACBCTL1 register before clearing the current stall flag (i.e., the SDAST,

NEGACK or STASTR bit of the ACBST register). This causes the ACB to send a Stop Condition immediately, and to clear

the STOP bit of the ACBCTL1 register. A Stop Condition may be issued only when the device is the active bus master (the

MASTER bit of the ACBST register is set).

Master Bus Stall

The ACB can stall the ACCESS.bus between transfers while waiting for the host response. The ACCESS.bus is stalled by

holding the SCL signal low after the acknowledge cycle. Note that this is interpreted as the beginning of the following bus

operation. The user must make sure that the next operation is prepared before the flag that causes the bus stall is cleared.

The flags that can cause a bus stall in master mode are:

Negative acknowledge after sending a byte (NEGACK bit of the ACBST register =1).

SDAST bit of the ACBST register =1.

STASTRE bit of the ACBCTL1 register =1, after a successful start (STASTR bit of the ACBST register =1).

Repeated Start

A repeated start is performed when the device is already the bus master (MASTER bit of the ACBST register is set). In this

case, the ACCESS.bus is stalled and the ACB awaits host handling due to the following states in the ACBST register: neg-

ative acknowledge (NEGACK bit =1), empty buffer (SDAST bit =1) and/or a stall after start (STASTR bit =1).

For a repeated start:

1. Set the START bit of the ACBCTL1 register =1.

2. In master receive mode, read the last data item from ACBSDA.

3. Follow the address send sequence, as described in “Sending the Address Byte”.

4. If the ACB was awaiting handling (STASTR bit of the ACBST register =1), clear it only after writing the requested address

and direction to ACBSDA.

Master Error Detection

The ACB detects illegal Start or Stop Conditions (i.e., a Start or Stop Condition within the data transfer, or the acknowledge

cycle) and a conflict on the data lines of the ACCESS.bus. If an illegal condition is detected, BER is set, and master mode

is exited (MASTER bit of the ACBST. register is cleared).

Bus Idle Error Recovery

When a request to become the active bus master or a restart operation fails, the BER bit of the ACBST register is set to

indicate the error. In some cases, both the device and the other device may identify the failure and leave the bus idle. In this

case, the start sequence may be incomplete and the ACCESS.bus may remain deadlocked.

To recover from deadlock, use the following sequence:

1. Clear the BER and BB bits of the ACBCST register.

2. Wait for a timeout period to check that there is no other active master on the bus (the BB bit remains cleared).

3. Disable, and re-enable the ACB to put it in the non-addressed slave mode. This completely resets the functional block.

At this point, some of the slaves may not identify the bus error. To recover, the ACB becomes the bus master: it asserts a

Start Condition, sends an address byte, then asserts a Stop Condition which synchronizes all the slaves.

PC87366 数据表(PDF) 146 Page - National Semiconductor (TI)

PC87366 数据表(HTML) 146 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载