PC87366 datasheet(144/240 Pages) NSC

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8.0 ACCESS.bus Interface (ACB) (Continued)

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8.2.4

Acknowledge after Every Byte Rule

According to this rule, the master generates an acknowledge clock pulse after each byte transfer, and the receiver sends an

acknowledge signal after every byte received. There are two exceptions to this rule:

1. When the master is the receiver, it must indicate to the transmitter the end of data by not acknowledging (negative ac-

knowledge) the last byte clocked out of the slave. This negative acknowledge still includes the acknowledge clock pulse

(generated by the master), but the SDA line is not pulled down.

2. When the receiver is full, otherwise occupied, or a problem has occurred, it sends a negative acknowledge to indicate

that it cannot accept additional data bytes.

8.2.5

Addressing Transfer Formats

Each device on the bus has a unique address. Before any data is transmitted, the master transmits the address of the slave

being addressed. The slave device should send an acknowledge signal on the SDA line once it recognizes its address.

The address consists of the first 7 bits after a Start Condition. The direction of the data transfer (R/W) depends on the bit

sent after the address, the eighth bit. A low to high transition during a SCL high period indicates the Stop Condition, and

ends the transaction of SDA (see Figure 26).

When the address is sent, each device in the system compares this address with its own. If there is a match, the device

considers itself addressed and sends an acknowledge signal. Depending on the state of the R/W bit (1=read, 0=write), the

device acts either as a transmitter or a receiver.

The I2C bus protocol allows a general call address to be sent to all slaves connected to the bus. The first byte sent specifies

the general call address (00h) and the second byte specifies the meaning of the general call (for example, write slave ad-

dress by software only). Those slaves that require data acknowledge the call, and become slave receivers; other slaves ig-

nore the call.

8.2.6

Arbitration on the Bus

Multiple master devices on the bus require arbitration between their conflicting bus access demands. Control of the bus is

initially determined according to address bits and clock cycle. If the masters are trying to address the same slave, data com-

parisons determine the outcome of this arbitration. In master mode, the device immediately aborts a transaction if the value

sampled on the SDA line differs from the value driven by the device. (An exception to this rule is SDA while receiving data.

The lines may be driven low by the slave without causing an abort.)

The SCL signal is monitored for clock synchronization and to allow the slave to stall the bus. The actual clock period is set

by the master with the longest clock period, or by the slave stall period. The clock high period is determined by the master

with the shortest clock high period.

When an abort occurs during the address transmission, a master that identifies the conflict should give up the bus, switch

to slave mode and continue to sample SDA to check if it is being addressed by the winning master on the bus.

Start

Condition

Stop

Condition

SDA

SCL

1 - 7

Address R/W ACK

Data

ACK

Data

ACK

Figure 26. A Complete ACCESS.bus Data Transaction

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