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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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PC87366 数据表(PDF) 143 Page - National Semiconductor (TI) |
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PC87366 数据表(HTML) 143 Page - National Semiconductor (TI) |
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143 / 240 page  8.0 ACCESS.bus Interface (ACB) (Continued) 143 www.national.com 8.2.3 Acknowledge (ACK) Cycle The ACK cycle consists of two signals: the ACK clock pulse sent by the master with each byte transferred, and the ACK signal sent by the receiving device (see Figure 24). The master generates the ACK clock pulse on the ninth clock pulse of the byte transfer. The transmitter releases the SDA line (permits it to go high) to allow the receiver to send the ACK signal. The receiver must pull down the SDA line during the ACK clock pulse, signalling that it has correctly received the last data byte and is ready to receive the next byte. Figure 25 illustrates the ACK cycle. SDA SCL S P Start Condition Stop Condition Figure 23. Start and Stop Conditions S P Start Condition Stop Condition SDA SCL MSB ACK ACK 12 3 - 6 7 8 9 1 2 3 - 8 9 Acknowledge Signal From Receiver Byte Complete Interrupt Within Receiver Clock Line Held Low by Receiver While Interrupt is Serviced Figure 24. ACCESS.bus Data Transaction S Start Condition SCL 12 3 - 6 7 8 9 Transmitter Stays Off Bus During Acknowledge Clock Acknowledge Signal From Receiver Data Output by Transmitter Data Output by Receiver Figure 25. ACCESS.bus Acknowledge Cycle |
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