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8.0

ACCESS.bus Interface (ACB)

The ACB is a two-wire synchronous serial interface compatible with the ACCESS.bus physical layer. The ACB is also com-

patible with Intel's SMBus and Philips’ I2C. The ACB can be configured as a bus master or slave, and can maintain bi-direc-

tional communication with both multiple master and slave devices. As a slave device, the ACB may issue a request to

become the bus master.

The ACB allows easy interfacing to a wide range of low-cost memories and I/O devices, including EEPROMs, SRAMs, tim-

ers, ADC, DAC, clock chips and peripheral drivers.

This chapter describes the general ACB functional block. A device may include a different implementation. For device spe-

cific implementation, see the

Device Architecture and Conﬁguration chapter.

8.1

OVERVIEW

The ACCESS.bus protocol uses a two-wire interface for bi-directional communication between the devices connected to the

bus. The two interface lines are the Serial Data Line (SDL) and the Serial Clock Line (SCL). These lines should be connected

to a positive supply via an internal or external pull-up resistor, and remain high even when the bus is idle.

Each IC has a unique address and can operate as a transmitter or a receiver (though some peripherals are only receivers).

During data transactions, the master device initiates the transaction, generates the clock signal and terminates the transac-

tion. For example, when the ACB initiates a data transaction with an attached ACCESS.bus compliant peripheral, the ACB

becomes the master. When the peripheral responds and transmits data to the ACB, their master/slave (data transaction ini-

tiator and clock generator) relationship is unchanged, even though their transmitter/receiver functions are reversed.

8.2

FUNCTIONAL DESCRIPTION

8.2.1

Data Transactions

One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock (SCL). Conse-

quently, throughout the clock’s high period, the data should remain stable (see Figure 22). Any changes on the SDA line

during the high state of the SCL and in the middle of a transaction aborts the current transaction. New data should be sent

during the low SCL state. This protocol permits a single data line to transfer both command/control information and data,

using the synchronous serial clock.

Each data transaction is composed of a Start Condition, a number of byte transfers (set by the software) and a Stop Condi-

tion to terminate the transaction. Each byte is transferred with the most significant bit first, and after each byte (8 bits), an

Acknowledge signal must follow. The following sections provide further details of this process.

During each clock cycle, the slave can stall the master while it handles the received data or prepares new data. This can be

done for each bit transferred, or on a byte boundary, by the slave holding SCL low to extend the clock-low period. Typically,

slaves extend the first clock cycle of a transfer if a byte read has not yet been stored, or if the next byte to be transmitted is

not yet ready. Some microcontrollers, with limited hardware support for ACCESS.bus, extend the access after each bit, thus

allowing the software to handle this bit.

8.2.2

Start and Stop Conditions

The ACCESS.bus master generates Start and Stop Conditions (control codes). After a Start Condition is generated, the bus

is considered busy and retains this status for a certain time after a Stop Condition is generated. A high to low transition of

the data line (SDA) while the clock (SCL) is high indicates a Start Condition. A low to high transition of the SDA line while

the SCL is high indicates a Stop Condition (Figure 23). After a Stop Condition is issued, the data in the received buffer is not

valid.

In addition to the first Start Condition, a repeated Start Condition can be generated in the middle of a transaction. This allows

another device to be accessed, or a change in the direction of data transfer.

SDA

SCL

Data Line

Stable:

Data Valid

Change

of Data

Allowed

Figure 22. Bit Transfer

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