PC87366 datasheet(145/240 Pages) NSC

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8.0 ACCESS.bus Interface (ACB) (Continued)

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8.2.7

Master Mode

Requesting Bus Mastership

An ACCESS.bus transaction starts with a master device requesting bus mastership. It asserts a Start Condition, followed

by the address of the device it wants to access. If this transaction is successfully completed, the software may assume that

the device has become the bus master.

For the device to become the bus master, the software should perform the following steps:

1. Configure the INTEN bit of the ACBCTL1 register to the desired operation mode (Polling or Interrupt) and set the START

bit of this register. This causes the ACB to issue a Start Condition on the ACCESS.bus when the ACCESS.bus becomes

free (BB bit of the ACBCST register is cleared, or other conditions that can delay start). It then stalls the bus by holding

SCL low.

2. If a bus conflict is detected (i.e., another device pulls down the SCL signal), the BER bit of the ACBST register is set.

3. If there is no bus conflict, the MASTER bit of the ACBST register and the SCAST of the ACBST register are set.

4. If the INTEN bit of the ACBCTL1 register is set and either the BER or SDAST bit of the ACBST register is set, an interrupt

is issued.

Sending the Address Byte

When the device is the active master of the ACCESS.bus (the MASTER bit of the ACBST register is set), it can send the

address on the bus.

The address sent should not be the device’s own address, as defined by the ADDR bit of the ACBADDR register if the SAEN

bit of this register is set, nor should it be the global call address if the GCMTCH bit of the ACBCST register is set.

To send the address byte, use the following sequence:

1. For a receive transaction where the software wants only one byte of data, it should set the ACB bit of the ACBCTL1

Registe. If only an address needs to be sent or if the device requires stall for some other reason, set the STASTRE bit

of the ACBCTL1 register.

2. Write the address byte (7-bit target device address) and the direction bit to the ACBSDA register. This causes the ACB

to generate a transaction. At the end of this transaction, the acknowledge bit received is copied to the NEGACK bit of

the ACBST register. During the transaction, the SDA and SCL lines are continuously checked for conflict with other de-

vices. If a conflict is detected, the transaction is aborted, the BER bit of the ACBST register is set and the MASTER bit

of this register is cleared.

3. If the STASTRE bit of the ACBCTL1 register is set and the transaction was successfully completed (i.e., both the BER

and NEGACK bits of the ACBST register are cleared), the STASTR bit is set. In this case, the ACB stalls any further

ACCESS.bus operations (i.e., holds SCL low). If the INTEN bit of the ACBCTL1 register is set, it also sends an interrupt

request to the host.

4. If the requested direction is transmit and the start transaction was completed successfully (i.e., neither the NEGACK nor

the BER bit of the ACBST register is set, and no other master has accessed the device), the SDAST bit of the ACBST

5. If the requested direction is receive, the start transaction was completed successfully and the STASTRE bit of the

ACBCTL1 register is cleared, the ACB starts receiving the first byte automatically.

6. Check that both the BER and NEGACK bits of the ACBST register are cleared. If the INTEN bit of the ACBCTL1 register

is set, an interrupt is generated when either the BER or NEGACK bit of the ACBST register is set.

Master Transmit

After becoming the bus master, the device can start transmitting data on the ACCESS.bus.

To transmit a byte in an interrupt or polling controlled operation, the software should:

1. Check that both the BER and NEGACK bits of the ACBST register are cleared, and that the SDAST bit of the ACBST

is cleared (and clear it if required).

2. Write the data byte to be transmitted to the ACBSDA register.

When either the NEGACK or BER bit of the ACBST register is set, an interrupt is generated. When the slave responds with

a negative acknowledge, the NEGACK bit of the ACBST register is set and the SDAST bit of the ACBST register remains

cleared. In this case, if the INTEN bit of the ACBCTL1 register is set, an interrupt is issued.

PC87366 数据表(PDF) 145 Page - National Semiconductor (TI)

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