ZUSBOPTSC01ZAC datasheet(129/402 Pages) ZILOG

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PS024604-1005

P R E L I M I N A R Y

Timer 0 Control Registers

Z8FMC16100 Series Flash MCU

Product Specification

107

Timer 0 Control 1 Register

The Timer 0 Control 1 (T0CTL1) Register, shown in Table 65, enables/disables the timer,

sets the prescaler value, and determines the timer operating mode.

[4]

TINSEL

Timer Input Select

Timer input is the Timer input pin.

Timer input is the comparator output.

[3–1]

PWMD

000

001

010

011

100

101

110

111

PWM Delay Value

This field is a programmable delay to control the number of additional system

clock cycles following a PWM or Reload compare before the Timer Output or the

Timer Output Complement is switched to the active state. This field ensures a

time gap between the deassertion of one PWM output to the assertion of its

complement.

No delay

2 cycles delay

4 cycles delay

8 cycles delay

16 cycles delay

32 cycles delay

64 cycles delay

128 cycles delay

[0]

INCAP

Input Capture Event

Previous timer interrupt is not a result of a Timer Input Capture Event

Previous timer interrupt is a result of a Timer Input Capture Event.

Table 65. Timer 0 Control 1 Register (T0CTL1)

BITS

FIELD

TEN

TPOL

PRES

TMODE

RESET

000

R/W

ADDR

F07H

Bit

Position

Value

(H)

Description

ZUSBOPTSC01ZAC 数据表(PDF) 129 Page - Zilog, Inc.

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