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Z8F021ASH020SC 数据表(PDF) 62 Page - Zilog, Inc.

部件名 Z8F021ASH020SC
功能描述  Z8 Encore XP-R 4K Series High-Performance 8-Bit Microcontrollers
PDF  276 Pages
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制造商  ZILOG [Zilog, Inc.]
网页  http://www.zilog.com
标志 ZILOG - Zilog, Inc.

Z8F021ASH020SC 数据表(HTML) 62 Page - Zilog, Inc.

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PS022815-0206
General-Purpose I/O
Z8 Encore! XP® 4K Series
Product Specification
43
functions as GPIO. If enabled, select one of four alternate functions using alternate func-
tion set subregisters 1 and 2 as described in the Port A–D Alternate Function Set 1 Sub-
Registers on page 45 and Port A–D Alternate Function Set 2 Sub-Registers on page 46.
Refer
to the GPIO Alternate Functions on page 33 to determine the alternate function asso-
ciated with each port pin.
Do not enable alternate functions for GPIO port pins for which there is no
associated alternate function. Failure to follow this guideline can result in
unpredictable operation.
AF[7:0]—Port Alternate Function enabled
0 = The port pin is in normal mode and the DDx bit in the Port A–D Data Direction sub-
register determines the direction of the pin.
1 = The alternate function selected through Alternate Function Set sub-registers is
enabled. Port pin operation is controlled by the alternate function.
Port A–D Output Control Sub-Registers
The Port A–D Output Control sub-register (Table 22) is accessed through the Port A–D
Control register by writing 03H to the Port A–D Address register. Setting the bits in the
Port A–D Output Control sub-registers to 1 configures the specified port pins for open-
drain operation. These sub-registers affect the pins directly and, as a result, alternate func-
tions are also affected.
POC[7:0]—Port Output Control
These bits function independently of the alternate function bit and always disable the
Table 21. Port A–D Alternate Function Sub-Registers (PxAF)
BITS
7
6
5
4
3
2
1
0
FIELD
AF7
AF6
AF5
AF4
AF3
AF2
AF1
AF0
RESET
00H (Ports A–C); 01H (Port D); 04H (Port A of 8-pin device)
R/W
R/W
ADDR
If 02H in Port A–D Address Register, accessible through the Port A–D Control Register
Table 22. Port A–D Output Control Sub-Registers (PxOC)
BITS
7
6
5
4
3
2
1
0
FIELD
POC7
POC6
POC5
POC4
POC3
POC2
POC1
POC0
RESET
0
000
00
00
R/W
R/WR/W
R/WR/W
R/WR/W
R/WR/W
ADDR
If 03H in Port A–D Address Register, accessible through the Port A–D Control Register
Caution:



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