Z8F021ASH020SC datasheet(73/276 Pages) ZILOG

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PS022815-0206

Interrupt Controller

Z8 Encore! XP® 4K Series

Product Specification

To avoid missing interrupts, use the following coding style to clear bits in the

Interrupt Request 0 register:

Good coding style that avoids lost interrupt requests:

ANDX IRQ0, MASK

Software Interrupt Assertion

Program code can generate interrupts directly. Writing a 1 to the correct bit in the Interrupt

Request register triggers an interrupt (assuming that interrupt is enabled). When the inter-

rupt request is acknowledged by the eZ8 CPU, the bit in the Interrupt Request register is

automatically cleared to 0.

The following coding style used to generate software interrupts by setting bits in the In-

terrupt Request registers is NOT recommended. All incoming interrupts received be-

tween execution of the first LDX command and the final LDX command are lost.

Poor coding style that can result in lost interrupt requests:

LDX r0, IRQ0

OR r0, MASK

LDX IRQ0, r0

To avoid missing interrupts, use the following coding style to set bits in the Interrupt Re-

quest registers:

Good coding style that avoids lost interrupt requests:

ORX IRQ0, MASK

Interrupt Control Register Definitions

For all interrupts other than the Watch-Dog Timer interrupt, the Primary Oscillator Fail

Trap, and the Watchdog Oscillator Fail Trap, the interrupt control registers enable individ-

ual interrupts, set interrupt priorities, and indicate interrupt requests.

Interrupt Request 0 Register

The Interrupt Request 0 (IRQ0) register (Table 34) stores the interrupt requests for both

vectored and polled interrupts. When a request is presented to the interrupt controller, the

corresponding bit in the IRQ0 register becomes 1. If interrupts are globally enabled (vec-

tored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If

Caution:

Z8F021ASH020SC 数据表(PDF) 73 Page - Zilog, Inc.