Z8F021ASH020SC datasheet(79/276 Pages) ZILOG

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PS022815-0206

Interrupt Controller

Z8 Encore! XP® 4K Series

Product Specification

C1ENH—Port C1 Interrupt Request Enable High Bit

C0ENH—Port C0 Interrupt Request Enable High Bit

Reserved—Must be 0.

C3ENL—Port C3 Interrupt Request Enable Low Bit

C2ENL—Port C2 Interrupt Request Enable Low Bit

C1ENL—Port C1 Interrupt Request Enable Low Bit

C0ENL—Port C0 Interrupt Request Enable Low Bit

Interrupt Edge Select Register

The Interrupt Edge Select (IRQES) register (Table 46) determines whether an interrupt is

generated for the rising edge or falling edge on the selected GPIO Port A or Port D input

pin.

IESx—Interrupt Edge Select x

0 = An interrupt request is generated on the falling edge of the PAx input or PDx.

1 = An interrupt request is generated on the rising edge of the PAx input PDx.

where x indicates the specific GPIO Port pin number (0 through 7).

Shared Interrupt Select Register

The Shared Interrupt Select (IRQSS) register (Table 47) determines the source of the

PADxS interrupts. The Shared Interrupt Select register selects between Port A and alter-

nate sources for the individual interrupts.

Table 45. IRQ2 Enable Low Bit Register (IRQ2ENL)

BITS

FIELD

Reserved

C3ENL

C2ENL

C1ENL

C0ENL

RESET

000

R/W

R/WR/W

ADDR

FC8H

Table 46. Interrupt Edge Select Register (IRQES)

BITS

FIELD

IES7

IES6

IES5

IES4

IES3

IES2

IES1

IES0

RESET

000

R/W

R/WR/W

ADDR

FCDH

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