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Z8F021ASH020SC 数据表(PDF) 47 Page - Zilog, Inc. |
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Z8F021ASH020SC 数据表(HTML) 47 Page - Zilog, Inc. |
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47 / 276 page  PS022815-0206 Reset, STOP Mode Recovery and Low Voltage Detection Z8 Encore! XP® 4K Series Product Specification 28 POR—Power-On Reset Indicator If this bit is set to 1, a Power-On Reset event occurred. This bit is reset to 0 if a WDT time- out or STOP Mode Recovery occurs. This bit is also reset to 0 when the register is read. STOP—STOP Mode Recovery Indicator If this bit is set to 1, a STOP Mode Recovery occurred. If the STOP and WDT bits are both set to 1, the STOP Mode Recovery occurred because of a WDT time-out. If the STOP bit is 1 and the WDT bit is 0, the STOP Mode Recovery was not caused by a WDT time-out. This bit is reset by a Power-On Reset or a WDT time-out that occurred while not in STOP mode. Reading this register also resets this bit. WDT—Watch-Dog Timer Time-Out Indicator If this bit is set to 1, a WDT time-out occurred. A Power-On Reset resets this pin. A STOP Mode Recovery from a change in an input pin also resets this bit. Reading this register resets this bit. This read must occur before clearing the WDT interrupt. EXT—External Reset Indicator If this bit is set to 1, a Reset initiated by the external RESET pin occurred. A Power-On Reset or a STOP Mode Recovery from a change in an input pin resets this bit. Reading this register resets this bit. Reserved—Must be 0. LVD—Low Voltage Detection Indicator If this bit is set to 1 the current state of the supply voltage is below the low voltage detec- tion threshold. This value is not latched but is a real-time indicator of the supply voltage level. Table 12. Reset Status Register (RSTSTAT) BITS 7 6 5 4 3 2 1 0 FIELD POR STOP WDT EXT Reserved LVD RESET See descriptions below 0 0 0 0 0 R/W R R R RRR RR ADDR FF0H Reset or STOP Mode Recovery Event POR STOP WDT EXT Power-On Reset 1000 Reset using RESET pin assertion 0001 Reset using Watch-Dog Timer time-out 0010 Reset using the On-Chip Debugger (OCTCTL[1] set to 1) 1000 Reset from STOP Mode using DBG Pin driven Low 1000 STOP Mode Recovery using GPIO pin transition 0100 STOP Mode Recovery using Watch-Dog Timer time-out 0110 |
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