Z8F021ASH020SC datasheet(60/276 Pages) ZILOG

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PS022815-0206

General-Purpose I/O

Z8 Encore! XP® 4K Series

Product Specification

Port A–D Address Registers

The Port A–D Address registers select the GPIO Port functionality accessible through the

Port A–D Control registers. The Port A–D Address and Control registers combine to pro-

vide access to all GPIO Port controls (Table 18).

PADDR[7:0]—Port Address

The Port Address selects one of the sub-registers accessible through the Port Control reg-

ister.

PxOC

Output Control (Open-Drain)

PxHDE

High Drive Enable

PxSMRE

STOP Mode Recovery Source Enable

PxPUE

Pull-up Enable

PxAFS1

Alternate Function Set 1

PxAFS2

Alternate Function Set 2

Table 18. Port A–D GPIO Address Registers (PxADDR)

BITS

FIELD

PADDR[7:0]

RESET

00H

R/W

R/WR/W

ADDR

FD0H, FD4H, FD8H, FDCH

PADDR[7:0] Port Control sub-register accessible using the Port A–D Control Registers

00H

No function. Provides some protection against accidental Port reconfiguration.

01H

Data Direction

02H

Alternate Function

03H

Output Control (Open-Drain)

04H

High Drive Enable

05H

STOP Mode Recovery Source Enable.

06H

Pull-up Enable

07H

Alternate Function Set 1

08H

Alternate Function Set 2

09H–FFH

No function

Table 17. GPIO Port Registers and Sub-Registers (Continued)

Port Register Mnemonic

Port Register Name

Z8F021ASH020SC 数据表(PDF) 60 Page - Zilog, Inc.

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