Z8F021ASH020SC datasheet(63/276 Pages) ZILOG

63 / 276 page

PS022815-0206

General-Purpose I/O

Z8 Encore! XP® 4K Series

Product Specification

drains if set to 1.

0 = The source current is enabled for any output mode (unless overridden by the alternate

function). (Push-pull output)

1 = The source current for the associated pin is disabled (open-drain mode).

Port A–D High Drive Enable Sub-Registers

The Port A–D High Drive Enable sub-register (Table 23) is accessed through the Port

A–D Control register by writing 04H to the Port A–D Address register. Setting the bits in

the Port A–D High Drive Enable sub-registers to 1 configures the specified port pins for

high current output drive operation. The Port A–D High Drive Enable sub-register affects

the pins directly and, as a result, alternate functions are also affected.

PHDE[7:0]—Port High Drive Enabled

0 = The Port pin is configured for standard output current drive.

1 = The Port pin is configured for high output current drive.

Port A–D STOP Mode Recovery Source Enable Sub-Registers

The Port A–D STOP Mode Recovery Source Enable sub-register (Table 24) is accessed

through the Port A–D Control register by writing 05H to the Port A–D Address register.

Setting the bits in the Port A–D STOP Mode Recovery Source Enable sub-registers to 1

configures the specified Port pins as a STOP Mode Recovery source. During STOP Mode,

any logic transition on a Port pin enabled as a STOP Mode Recovery source initiates

STOP Mode Recovery.

PSMRE[7:0]—Port STOP Mode Recovery Source Enabled

0 = The Port pin is not configured as a STOP Mode Recovery source. Transitions on this

Table 23. Port A–D High Drive Enable Sub-Registers (PxHDE)

BITS

FIELD

PHDE7

PHDE6

PHDE5

PHDE4

PHDE3

PHDE2

PHDE1

PHDE0

RESET

000

R/W

R/WR/W

ADDR

If 04H in Port A–D Address Register, accessible through the Port A–D Control Register

Table 24. Port A–D STOP Mode Recovery Source Enable Sub-Registers (PxSMRE)

BITS

FIELD

PSMRE7

PSMRE6

PSMRE5

PSMRE4

PSMRE3

PSMRE2

PSMRE1

PSMRE0

RESET

000

R/W

R/WR/W

ADDR

If 05H in Port A–D Address Register, accessible through the Port A–D Control Register

Z8F021ASH020SC 数据表(PDF) 63 Page - Zilog, Inc.

Z8F021ASH020SC 数据表(HTML) 63 Page - Zilog, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载