Z8F021ASH020SC datasheet(97/276 Pages) ZILOG

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PS022815-0206

Timers

Z8 Encore! XP® 4K Series

Product Specification

PWMH and PWML—Pulse-Width Modulator High and Low Bytes

These two bytes, {PWMH[7:0], PWML[7:0]}, form a 16-bit value that is compared to the

current 16-bit timer count. When a match occurs, the PWM output changes state. The

PWM output value is set by the TPOL bit in the Timer Control Register (TxCTL1) regis-

ter.

The TxPWMH and TxPWML registers also store the 16-bit captured timer value when

operating in Capture or Capture/Compare modes.

Timer 0–1 Control Registers

Time 0–1 Control Register 0

The Timer Control Register 0 (TxCTL0) and Timer Control Register 1 (TxCTL1) deter-

mine the timer operating mode. It also includes a programmable PWM deadband delay,

two bits to configure timer interrupt definition, and a status bit to identify if the most

recent timer interrupt is caused by an input capture event.

TMODEHI—Timer Mode High Bit

This bit along with the TMODE field in TxCTL1 register determines the operating mode

of the timer. This is the most significant bit of the Timer mode selection value. See the

TxCTL1 register description for details of the full timer mode decoding.

TICONFIG—Timer Interrupt Configuration

This field configures timer interrupt definition.

Table 54. Timer 0–1 PWM Low Byte Register (TxPWML)

BITS

FIELD

PWML

RESET

000

R/W

R/WR/W

ADDR

F05H, F0DH

Table 55. Timer 0–1 Control Register 0 (TxCTL0)

BITS

FIELD

TMODEHI

TICONFIG

Reserved

PWMD

INPCAP

RESET

000

R/W

R/WR/W

R/W

ADDR

F06H, F0EH

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