Z8F021ASH020SC datasheet(77/276 Pages) ZILOG

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PS022815-0206

Interrupt Controller

Z8 Encore! XP® 4K Series

Product Specification

T1ENL—Timer 1 Interrupt Request Enable Low Bit

T0ENL—Timer 0 Interrupt Request Enable Low Bit

U0RENL—UART 0 Receive Interrupt Request Enable Low Bit

U0TENL—UART 0 Transmit Interrupt Request Enable Low Bit

ADCENL—ADC Interrupt Request Enable Low Bit

IRQ1 Enable High and Low Bit Registers

Table 40 describes the priority control for IRQ1. The IRQ1 Enable High and Low Bit reg-

isters (Tables 41 and 42) form a priority encoded enabling for interrupts in the Interrupt

Request 1 register.

PA7VENH—Port A Bit[7] or LVD Interrupt Request Enable High Bit

PA6CENH—Port A Bit[7] or Comparator Interrupt Request Enable High Bit

PAxENH—Port A Bit[x] Interrupt Request Enable High Bit

Refer to the Shared Interrupt Select (IRQSS) register for selection of either the LVD or the

comparator as the interrupt source.

Table 40. IRQ1 Enable and Priority Encoding

IRQ1ENH[x]IRQ1ENL[x] Priority

Description

Disabled

Level 1

Low

Level 2

Medium

Level 3

High

where x indicates the register bits from 0–7.

Table 41. IRQ1 Enable High Bit Register (IRQ1ENH)

BITS

FIELD

PA7VENH PA6CENH PA5ENH

PA4ENH

PA3ENH

PA2ENH

PA1ENH

PA0ENH

RESET

000

R/W

R/WR/W

ADDR

FC4H

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