Z8F021ASH020SC datasheet(88/276 Pages) ZILOG

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PS022815-0206

Timers

Z8 Encore! XP® 4K Series

Product Specification

PWM DUAL OUTPUT Mode

In PWM DUAL OUTPUT mode, the timer outputs a Pulse-Width Modulated (PWM) out-

put signal pair (basic PWM signal and its complement) through two GPIO Port pins. The

timer input is the system clock. The timer first counts up to the 16-bit PWM match value

stored in the Timer PWM High and Low Byte registers. When the timer count value

matches the PWM value, the Timer Output toggles. The timer continues counting until it

reaches the Reload value stored in the Timer Reload High and Low Byte registers. Upon

reaching the Reload value, the timer generates an interrupt, the count value in the Timer

High and Low Byte registers is reset to 0001H and counting resumes.

If the TPOL bit in the Timer Control register is set to 1, the Timer Output signal begins as

a High (1) and transitions to a Low (0) when the timer value matches the PWM value. The

Timer Output signal returns to a High (1) after the timer reaches the Reload value and is

reset to 0001H.

If the TPOL bit in the Timer Control register is set to 0, the Timer Output signal begins as

a Low (0) and transitions to a High (1) when the timer value matches the PWM value. The

Timer Output signal returns to a Low (0) after the timer reaches the Reload value and is

reset to 0001H.

The timer also generates a second PWM output signal Timer Output Complement. The

Timer Output Complement is the complement of the Timer Output PWM signal. A pro-

grammable deadband delay can be configured to time delay (0 to 128 system clock cycles)

PWM output transitions on these two pins from a low to a high (inactive to active). This

ensures a time gap between the deassertion of one PWM output to the assertion of its com-

plement.

The steps for configuring a timer for PWM DUAL OUTPUT mode and initiating the

PWM operation are as follows:

1. Write to the Timer Control register to:

–

Disable the timer

–

Configure the timer for PWM DUAL OUTPUT mode by writing the TMODE bits

in the TxCTL1 register and theTMODEHI bit in TxCTL0 register.

–

Set the prescale value.

–

Set the initial logic level (High or Low) and PWM High/Low transition for the

Timer Output alternate function.

2. Write to the Timer High and Low Byte registers to set the starting count value

(typically 0001H). This only affects the first pass in PWM mode. After the first timer

reset in PWM mode, counting always begins at the reset value of 0001H.

3. Write to the PWM High and Low Byte registers to set the PWM value.

4. Write to the PWM Control register to set the PWM dead band delay value. The

deadband delay must be less than the duration of the positive phase of the PWM signal

(as defined by the PWM high and low byte registers). It must also be less than the

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