Z8F021ASH020SC datasheet(74/276 Pages) ZILOG

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PS022815-0206

Interrupt Controller

Z8 Encore! XP® 4K Series

Product Specification

interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt

Request 0 register to determine if any interrupt requests are pending.

Reserved—Must be 0.

T1I—Timer 1 Interrupt Request

0 = No interrupt request is pending for Timer 1.

1 = An interrupt request from Timer 1 is awaiting service.

T0I—Timer 0 Interrupt Request

0 = No interrupt request is pending for Timer 0.

1 = An interrupt request from Timer 0 is awaiting service.

U0RXI—UART 0 Receiver Interrupt Request

0 = No interrupt request is pending for the UART 0 receiver.

1 = An interrupt request from the UART 0 receiver is awaiting service.

U0TXI—UART 0 Transmitter Interrupt Request

0 = No interrupt request is pending for the UART 0 transmitter.

1 = An interrupt request from the UART 0 transmitter is awaiting service.

ADCI—ADC Interrupt Request

0 = No interrupt request is pending for the Analog-to-Digital Converter.

1 = An interrupt request from the Analog-to-Digital Converter is awaiting service.

Interrupt Request 1 Register

The Interrupt Request 1 (IRQ1) register (Table 35) stores interrupt requests for both vec-

tored and polled interrupts. When a request is presented to the interrupt controller, the cor-

responding bit in the IRQ1 register becomes 1. If interrupts are globally enabled (vectored

interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If interrupts

are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt Request 1

Table 34. Interrupt Request 0 Register (IRQ0)

BITS

FIELD

Reserved

T1I

T0I

U0RXI

U0TXI

Reserved Reserved

ADCI

RESET

000

R/W

R/WR/W

ADDR

FC0H

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