Z8F021ASH020SC datasheet(76/276 Pages) ZILOG

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PS022815-0206

Interrupt Controller

Z8 Encore! XP® 4K Series

Product Specification

IRQ0 Enable High and Low Bit Registers

Table 37 describes the priority control for IRQ0. The IRQ0 Enable High and Low Bit reg-

isters (Tables 38 and 39) form a priority encoded enabling for interrupts in the Interrupt

Request 0 register.

Reserved—Must be 0.

T1ENH—Timer 1 Interrupt Request Enable High Bit

T0ENH—Timer 0 Interrupt Request Enable High Bit

U0RENH—UART 0 Receive Interrupt Request Enable High Bit

U0TENH—UART 0 Transmit Interrupt Request Enable High Bit

ADCENH—ADC Interrupt Request Enable High Bit

Reserved—Must be 0.

Table 37. IRQ0 Enable and Priority Encoding

IRQ0ENH[x] IRQ0ENL[x] Priority

Description

Disabled

Level 1

Low

Level 2

Medium

Level 3

High

where x indicates the register bits from 0–7.

Table 38. IRQ0 Enable High Bit Register (IRQ0ENH)

BITS

FIELD

Reserved

T1ENH

T0ENH

U0RENH

U0TENH

Reserved Reserved ADCENH

RESET

000

R/W

R/WR/W

ADDR

FC1H

Table 39. IRQ0 Enable Low Bit Register (IRQ0ENL)

BITS

FIELD

Reserved

T1ENL

T0ENL

U0RENL

U0TENL

Reserved Reserved

ADCENL

RESET

000

R/W

ADDR

FC2H

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