Z8F021ASH020SC datasheet(98/276 Pages) ZILOG

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PS022815-0206

Timers

Z8 Encore! XP® 4K Series

Product Specification

0x = Timer Interrupt occurs on all defined Reload, Compare and Input Events

10 = Timer Interrupt only on defined Input Capture/Deassertion Events

11 = Timer Interrupt only on defined Reload/Compare Events

Reserved—Must be 0.

PWMD—PWM Delay value

This field is a programmable delay to control the number of system clock cycles delay

before the Timer Output and the Timer Output Complement are forced to their active state.

000 = No delay

001 = 2 cycles delay

010 = 4 cycles delay

011 = 8 cycles delay

100 = 16 cycles delay

101 = 32 cycles delay

110 = 64 cycles delay

111 = 128 cycles delay

INPCAP—Input Capture Event

This bit indicates if the most recent timer interrupt is caused by a Timer Input Capture

Event.

0 = Previous timer interrupt is not a result of Timer Input Capture Event

1 = Previous timer interrupt is a result of Timer Input Capture Event

Timer 0–1 Control Register 1

The Timer 0–1 Control (TxCTL1) registers enable/disable the timers, set the prescaler

value, and determine the timer operating mode.

TEN—Timer Enable

0 = Timer is disabled.

1 = Timer enabled to count.

TPOL—Timer Input/Output Polarity

Operation of this bit is a function of the current operating mode of the timer.

ONE-SHOT mode

When the timer is disabled, the Timer Output signal is set to the value of this bit.

Table 56. Timer 0–1 Control Register 1 (TxCTL1)

BITS

FIELD

TEN

TPOL

PRES

TMODE

RESET

000

R/W

R/WR/W

ADDR

F07H, F0FH

Z8F021ASH020SC 数据表(PDF) 98 Page - Zilog, Inc.

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