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Z8F021ASH020SC 数据表(PDF) 71 Page - Zilog, Inc. |
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Z8F021ASH020SC 数据表(HTML) 71 Page - Zilog, Inc. |
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71 / 276 page  PS022815-0206 Interrupt Controller Z8 Encore! XP® 4K Series Product Specification 52 Architecture Figure 8 illustrates the interrupt controller block diagram. Figure 8.Interrupt Controller Block Diagram Operation Master Interrupt Enable The master interrupt enable bit (IRQE) in the Interrupt Control register globally enables and disables interrupts. Interrupts are globally enabled by any of the following actions: • Execution of an EI (Enable Interrupt) instruction • Execution of an IRET (Return from Interrupt) instruction Lowest 0036H Port C0, both input edges 0038H Reserved Table 33. Trap and Interrupt Vectors in Order of Priority (Continued) Priority Program Memory Vector Address Interrupt or Trap Source Vector IRQ Request High Priority Medium Priority Low Priority Priority Mux Port Interrupts Internal Interrupts |
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