Z8F021ASH020SC datasheet(92/276 Pages) ZILOG

92 / 276 page

PS022815-0206

Timers

Z8 Encore! XP® 4K Series

Product Specification

the Timer Output pin changes state (from Low to High or from High to Low) upon Com-

pare.

If the Timer reaches FFFFH, the timer rolls over to 0000H and continue counting.

The steps for configuring a timer for COMPARE mode and initiating the count are as fol-

lows:

1. Write to the Timer Control register to:

–

Disable the timer

–

Configure the timer for COMPARE mode.

–

Set the prescale value.

–

Set the initial logic level (High or Low) for the Timer Output alternate function, if

appropriate.

2. Write to the Timer High and Low Byte registers to set the starting count value.

3. Write to the Timer Reload High and Low Byte registers to set the Compare value.

4. Enable the timer interrupt, if appropriate, and set the timer interrupt priority by writing

to the relevant interrupt registers.

5. If using the Timer Output function, configure the associated GPIO port pin for the

Timer Output alternate function.

6. Write to the Timer Control register to enable the timer and initiate counting.

In Compare mode, the system clock always provides the timer input. The Compare time

can be calculated by the following equation:

GATED Mode

In GATED mode, the timer counts only when the Timer Input signal is in its active state

(asserted), as determined by the TPOL bit in the Timer Control register. When the Timer

Input signal is asserted, counting begins. A timer interrupt is generated when the Timer

Input signal is deasserted or a timer reload occurs. To determine if a Timer Input signal

deassertion generated the interrupt, read the associated GPIO input value and compare to

the value stored in the TPOL bit.

The timer counts up to the 16-bit Reload value stored in the Timer Reload High and Low

Byte registers. The timer input is the system clock. When reaching the Reload value, the

timer generates an interrupt, the count value in the Timer High and Low Byte registers is

reset to 0001H and counting resumes (assuming the Timer Input signal remains asserted).

Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state

(from Low to High or from High to Low) at timer reset.

The steps for configuring a timer for GATED mode and initiating the count are as follows:

Compare Mode Time (s)

Compare Value Start Value

–

() Prescale

System Clock Frequency (Hz)

-------------------------------------------------------------------------------------------------------

Z8F021ASH020SC 数据表(PDF) 92 Page - Zilog, Inc.

Z8F021ASH020SC 数据表(HTML) 92 Page - Zilog, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载