Z8F021ASH020SC datasheet(40/276 Pages) ZILOG

40 / 276 page

PS022815-0206

Reset, STOP Mode Recovery and Low Voltage Detection

Z8 Encore! XP® 4K Series

Product Specification

During a System Reset or STOP Mode Recovery, the Internal Precision Oscillator requires

4 µs to start up. Then the Z8 Encore! XP® 4K Series device is held in Reset for 66 cycles

of the Internal Precision Oscillator. If the crystal oscillator is enabled in the Flash option

bits, this reset period is increased to 5000 IPO cycles. When a reset occurs because of a

low voltage condition or power on reset, this delay is measured from the time that the sup-

ply voltage first exceeds the POR level (discussed later in this chapter). If the external pin

reset remains asserted at the end of the reset period, the device remains in reset until the

pin is deasserted.

At the beginning of Reset, all GPIO pins are configured as inputs with pull-up resistor dis-

abled, except PD0 (or PA2 on 8-pin devices) which is shared with the reset pin. On reset,

the Port D0 pin is configured as a bidirectional open-drain reset. The pin is internally

driven low during port reset, after which the user code may reconfigure this pin as a gen-

eral purpose output.

During Reset, the eZ8 CPU and on-chip peripherals are idle; however, the on-chip crystal

oscillator and Watch-Dog Timer oscillator continue to run.

Upon Reset, control registers within the Register File that have a defined Reset value are

loaded with their reset values. Other control registers (including the Stack Pointer, Regis-

ter Pointer, and Flags) and general-purpose RAM are undefined following Reset. The eZ8

CPU fetches the Reset vector at Program Memory addresses 0002H and 0003H and loads

that value into the Program Counter. Program execution begins at the Reset vector

address.

Because the control registers are re-initialized by a system reset, the system clock after

reset is always the IPO. User software must reconfigure the oscillator control block, such

that the correct system clock source is enabled and selected.

Table 9. Reset and STOP Mode Recovery Characteristics and Latency

Reset Type

Reset Characteristics and Latency

Control Registers

eZ8

CPU

Reset Latency (Delay)

System Reset

Reset (as applicable)

Reset 66 Internal Precision Oscillator Cycles

System Reset with Crystal

Oscillator Enabled

Reset (as applicable)

Reset 5000 Internal Precision Oscillator Cycles

STOP Mode Recovery

Unaffected, except

WDT_CTL and

OSC_CTL registers

Reset 66 Internal Precision Oscillator Cycles

+ IPO startup time

STOP Mode Recovery with

Crystal Oscillator Enabled

Unaffected, except

WDT_CTL and

OSC_CTL registers

Reset 5000 Internal Precision Oscillator Cycles

Z8F021ASH020SC 数据表(PDF) 40 Page - Zilog, Inc.

Z8F021ASH020SC 数据表(HTML) 40 Page - Zilog, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载