Z8F021ASH020SC datasheet(114/276 Pages) ZILOG

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PS022815-0206

UART

Z8 Encore! XP® 4K Series

Product Specification

4. Executes the IRET instruction to return from the interrupt-service routine and await

more data.

Clear To Send (CTS) Operation

The CTS pin, if enabled by the CTSE bit of the UART Control 0 register, performs flow

control on the outgoing transmit datastream. The Clear To Send (CTS) input pin is sam-

pled one system clock before beginning any new character transmission. To delay trans-

mission of the next data character, an external receiver must deassert CTS at least one

system clock cycle before a new data transmission begins. For multiple character trans-

missions, this action is typically performed during Stop Bit transmission. If CTS deasserts

in the middle of a character transmission, the current character is sent completely.

MULTIPROCESSOR (9-bit) Mode

The UART has a MULTIPROCESSOR (9-bit) mode that uses an extra (9th) bit for selec-

tive communication when a number of processors share a common UART bus. In MULTI-

PROCESSOR mode (also referred to as 9-Bit mode), the multiprocessor bit (MP) is

transmitted immediately following the 8-bits of data and immediately preceding the Stop

bit(s) as illustrated in Figure 13. The character format is:

Figure 13.UART Asynchronous MULTIPROCESSOR Mode Data Format

In MULTIPROCESSOR (9-bit) mode, the Parity bit location (9th bit) becomes the Multi-

processor control bit. The UART Control 1 and Status 1 registers provide MULTIPRO-

CESSOR (9-bit) mode control and status information. If an automatic address matching

scheme is enabled, the UART Address Compare register holds the network address of the

device.

MULTIPROCESSOR (9-bit) Mode Receive Interrupts

When MULTIPROCESSOR mode is enabled, the UART only processes frames addressed

to it. The determination of whether a frame of data is addressed to the UART can be made

in hardware, software or some combination of the two, depending on the multiprocessor

configuration bits. In general, the address compare feature reduces the load on the CPU,

because it does not require access to the UART when it receives data directed to other

Start

Bit0

Bit1

Bit2

Bit3

Bit4

Bit5

Bit6

Bit7

Data Field

lsb

msb

Idle State

of Line

Stop Bit(s)

Z8F021ASH020SC 数据表(PDF) 114 Page - Zilog, Inc.

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