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EDBA164B4PR-1DITF-R 数据表(PDF) 103 Page - Micron Technology |
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EDBA164B4PR-1DITF-R 数据表(HTML) 103 Page - Micron Technology |
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103 / 152 page  Electrical Specifications – IDD Specifications and Conditions The following definitions and conditions are used in the IDD measurement tables unless stated otherwise: • LOW: VIN ≤ VIL(DC)max • HIGH: VIN ≥ VIH(DC)min • STABLE: Inputs are stable at a HIGH or LOW level • SWITCHING: See the following three tables Table 61: Switching for CA Input Signals Notes 1–3 apply to all parameters and conditions CK_t Rising/ CK_c Fall- ing CK_t Fall- ing/ CK_c Rising CK_t Rising/ CK_c Fall- ing CK_t Fall- ing/ CK_c Rising CK_t Rising/ CK_c Fall- ing CK_t Fall- ing/ CK_c Rising CK_t Rising/ CK_c Fall- ing CK_t Fall- ing/ CK_c Rising Cycle N N + 1 N + 2 N + 3 CS_n HIGH HIGH HIGH HIGH CA0 H L L L L H H H CA1 H H H L L L L H CA2 H L L L L H H H CA3 H H H L L L L H CA4 H L L L L H H H CA5 H H H L L L L H CA6 H L L L L H H H CA7 H H H L L L L H CA8 H L L L L H H H CA9 H H H L L L L H Notes: 1. CS# must always be driven HIGH. 2. For each clock cycle, 50% of the CA bus is changing between HIGH and LOW. 3. The noted pattern (N, N + 1, N + 2, N + 3...) is used continuously during IDD measure- ment for IDD values that require switching on the CA bus. Table 62: Switching for IDD4R Clock CKE CS_n Clock Cycle Number Command CA[2:0] CA[9:3] All DQ Rising H L N Read_Rising HLH LHLHLHL L Falling H L N Read_Falling LLL LLLLLLL L Rising H H N +1 NOP LLL LLLLLLL H Falling H H N + 1 NOP HLH HLHLLHL L Rising H L N + 2 Read_Rising HLH HLHLLHL H Falling H L N + 2 Read_Falling LLL HHHHHHH H Rising H H N + 3 NOP LLL HHHHHHH H 216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM Electrical Specifications – IDD Specifications and Conditions 09005aef85eb530a 216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN 103 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. |
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