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Table 64: IDD Specification Parameters and Operating Conditions (Continued)

Notes 1–3 apply to all parameters and conditions

Parameter/Condition

Symbol

Power Supply

Notes

Deep power-down current: CK_t = LOW, CK_c = HIGH; CKE is LOW; CA bus

inputs are stable; Data bus inputs are stable

IDD81

VDD1

IDD82

VDD2

IDD8IN

VDDQ

4, 7

Notes:

1. IDD values are the maximum of the distribution of the arithmetic mean.

2. IDD current specifications are tested after the device is properly initialized.

3. The 1x self refresh rate is the rate at which the device is refreshed internally during self

refresh before going into the extended temperature range.

4. Measured currents are the sum of VDDQ and VDD2.

5. Per-bank REFRESH is only applicable for LPDDR2-S4 device densities 1Gb or higher.

6. This is the general definition that applies to full-array self refresh. Refer to "IDD6 Full

and Partial Array Self-Refresh Current" for details of Partial Array Self Refresh IDD6

specification.

7. IDD6ET and IDD8 are typical values, sampled only and not tested.

AC and DC Operating Conditions

An operation or timing that is not specified is illegal. To ensure proper operation, the

device must be initialized properly.

Table 65: Recommended DC Operating Conditions

Symbol

LPDDR2-S4B

Power Supply

Unit

Min

Typ

Max

VDD11

1.70

1.80

1.95

Core power 1

VDD2

1.14

1.20

1.30

Core power 2

VDDQ

1.14

1.20

1.30

I/O buffer power

Note:

1. VDD1 uses significantly less power than VDD2.

Table 66: Input Leakage Current

Parameter/Condition

Symbol

Min

Max

Unit

Notes

Input leakage current: For CA, CKE, CS_n, CK_t, CK_c; Any input 0V

≤

VIN ≤ VDD2; (All other pins not under test = 0V)

–2

μA1

VREF supply leakage current: VREFDQ = VDDQ/2, or VREFCA = VDD2/2; (All

other pins not under test = 0V)

IVREF

–1

μA2

Notes:

1. Although DM is for input only, the DM leakage must match the DQ and DQS_t/DQS_c

output leakage specification.

2. The minimum limit requirement is for testing purposes. The leakage current on VREFCA

and VREFDQ pins should be minimal.

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

AC and DC Operating Conditions

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

106

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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